Searched refs:CSR_WRITE_1 (Results 1 - 25 of 48) sorted by relevance

12

/freebsd-11-stable/sys/dev/ex/
H A Dif_ex.c328 CSR_WRITE_1(sc, CMD_REG, Bank2_Sel);
331 CSR_WRITE_1(sc, EEPROM_REG, temp_reg & ~Trnoff_Enable);
333 CSR_WRITE_1(sc, I_ADDR_REG0 + i, IF_LLADDR(sc->ifp)[i]);
341 CSR_WRITE_1(sc, REG1, CSR_READ_1(sc, REG1) | Tx_Chn_Int_Md | Tx_Chn_ErStp | Disc_Bad_Fr);
342 CSR_WRITE_1(sc, REG2, CSR_READ_1(sc, REG2) | No_SA_Ins | RX_CRC_InMem);
343 CSR_WRITE_1(sc, REG3, CSR_READ_1(sc, REG3) & 0x3f /* XXX constants. */ );
349 CSR_WRITE_1(sc, CMD_REG, Bank1_Sel);
351 CSR_WRITE_1(sc, INT_NO_REG,
366 CSR_WRITE_1(sc, RCV_LOWER_LIMIT_REG, sc->rx_lower_limit >> 8);
367 CSR_WRITE_1(s
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H A Dif_ex_isa.c154 CSR_WRITE_1(&sc, CMD_REG, Reset_CMD);
166 CSR_WRITE_1(&sc, CMD_REG, Reset_CMD);
234 CSR_WRITE_1(sc, CMD_REG, Reset_CMD);
H A Dif_exvar.h97 #define CSR_WRITE_1(sc, off, val) \ macro
/freebsd-11-stable/sys/dev/vge/
H A Dif_vge.c253 CSR_WRITE_1(sc, VGE_EEADDR, addr);
310 CSR_WRITE_1(sc, VGE_MIICMD, 0);
329 CSR_WRITE_1(sc, VGE_MIICMD, 0);
330 CSR_WRITE_1(sc, VGE_MIIADDR, VGE_MIIADDR_SWMPL);
345 CSR_WRITE_1(sc, VGE_MIICMD, VGE_MIICMD_MAUTO);
371 CSR_WRITE_1(sc, VGE_MIIADDR, reg);
404 CSR_WRITE_1(sc, VGE_MIIADDR, reg);
442 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE);
444 CSR_WRITE_1(sc, VGE_CAM0 + i, 0);
448 CSR_WRITE_1(s
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H A Dif_vgevar.h221 #define CSR_WRITE_1(sc, reg, val) \ macro
232 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x))
239 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x))
/freebsd-11-stable/sys/dev/sn/
H A Dif_sn.c313 CSR_WRITE_1(sc, INTR_MASK_REG_B, 0x00);
342 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask);
471 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask);
491 CSR_WRITE_1(sc, PACKET_NUM_REG_B, packet_no);
503 CSR_WRITE_1(sc, DATA_REG_B, (length + 6) & 0xFF);
504 CSR_WRITE_1(sc, DATA_REG_B, (length + 6) >> 8);
527 CSR_WRITE_1(sc, DATA_REG_B,
539 CSR_WRITE_1(sc, DATA_REG_B, 0);
553 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask);
674 CSR_WRITE_1(s
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H A Dif_snvar.h60 #define CSR_WRITE_1(sc, off, val) \ macro
/freebsd-11-stable/sys/dev/vr/
H A Dif_vr.c250 CSR_WRITE_1(sc, VR_MIIADDR, reg);
273 CSR_WRITE_1(sc, VR_MIIADDR, reg);
344 CSR_WRITE_1(sc, VR_CR1, cr1);
359 CSR_WRITE_1(sc, VR_FLOWCR1, fc);
367 CSR_WRITE_1(sc, VR_MISC_CR0, fc);
387 CSR_WRITE_1(sc, VR_CAMCTL, VR_CAMCTL_ENA | VR_CAMCTL_MCAST);
389 CSR_WRITE_1(sc, VR_CAMCTL, VR_CAMCTL_ENA | VR_CAMCTL_VLAN);
391 CSR_WRITE_1(sc, VR_CAMCTL, 0);
402 CSR_WRITE_1(sc, VR_CAMCTL, VR_CAMCTL_ENA | VR_CAMCTL_MCAST);
404 CSR_WRITE_1(s
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H A Dif_vrreg.h753 #define CSR_WRITE_1(sc, reg, val) bus_write_1(sc->vr_res, reg, val) macro
758 #define VR_SETBIT(sc, reg, x) CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x))
759 #define VR_CLRBIT(sc, reg, x) CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x))
/freebsd-11-stable/sys/dev/vx/
H A Dif_vxvar.h64 #define CSR_WRITE_1(sc, reg, val) \ macro
/freebsd-11-stable/sys/dev/re/
H A Dif_re.c351 CSR_WRITE_1(sc, RL_EECMD, \
355 CSR_WRITE_1(sc, RL_EECMD, \
728 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET);
739 CSR_WRITE_1(sc, 0x82, 1);
1314 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
1317 CSR_WRITE_1(sc, RL_CFG2, cfg);
1318 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
1351 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
1356 CSR_WRITE_1(sc, RL_CFG2, cfg);
1358 CSR_WRITE_1(s
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/freebsd-11-stable/sys/dev/rl/
H A Dif_rl.c266 CSR_WRITE_1(sc, RL_EECMD, \
270 CSR_WRITE_1(sc, RL_EECMD, \
310 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
317 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
332 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
384 CSR_WRITE_1(sc, RL_MII, val);
568 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET);
1717 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG);
1722 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
1735 CSR_WRITE_1(s
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/freebsd-11-stable/sys/dev/msk/
H A Dif_msk.c512 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_MSK),
1253 CSR_WRITE_1(sc, B0_POWER_CTRL,
1269 CSR_WRITE_1(sc, B2_Y2_CLK_GATE, val);
1337 CSR_WRITE_1(sc, B2_Y2_CLK_GATE, val);
1338 CSR_WRITE_1(sc, B0_POWER_CTRL,
1370 CSR_WRITE_1(sc, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
1382 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON);
1419 CSR_WRITE_1(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_SET);
1420 CSR_WRITE_1(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_CLR);
1439 CSR_WRITE_1(s
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/freebsd-11-stable/sys/dev/bm/
H A Dif_bmreg.h159 #define CSR_WRITE_1(sc, reg, val) \ macro
/freebsd-11-stable/sys/dev/tx/
H A Dif_txvar.h134 #define CSR_WRITE_1(sc, reg, val) \ macro
/freebsd-11-stable/sys/dev/ep/
H A Dif_epvar.h88 #define CSR_WRITE_1(sc, off, val) \ macro
H A Dif_ep.c276 CSR_WRITE_1(sc, EP_W2_ADDR_0 + i, enaddr[i]);
557 CSR_WRITE_1(sc, EP_W1_TX_PIO_WR_1,
563 CSR_WRITE_1(sc, EP_W1_TX_PIO_WR_1, 0); /* Padding */
703 CSR_WRITE_1(sc, EP_W1_TX_STATUS, 0x0);
/freebsd-11-stable/sys/dev/fxp/
H A Dif_fxpvar.h247 #define CSR_WRITE_1(sc, reg, val) bus_write_1(sc->fxp_res[0], reg, val) macro
/freebsd-11-stable/sys/dev/ipw/
H A Dif_ipwreg.h334 #define CSR_WRITE_1(sc, reg, val) \ macro
360 CSR_WRITE_1((sc), IPW_CSR_INDIRECT_DATA, (val)); \
/freebsd-11-stable/sys/dev/ste/
H A Dif_ste.c197 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x))
200 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x))
230 CSR_WRITE_1(sc, STE_PHYCTL, val);
452 CSR_WRITE_1(sc, STE_RX_MODE, rxcfg);
1537 CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 64);
1546 CSR_WRITE_1(sc, STE_WAKE_EVENT, val);
1549 CSR_WRITE_1(sc, STE_TX_DMABURST_THRESH, STE_PACKET_SIZE >> 8);
1555 CSR_WRITE_1(sc, STE_TX_RECLAIM_THRESH, (STE_PACKET_SIZE >> 4));
1572 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0);
1641 CSR_WRITE_1(s
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/freebsd-11-stable/sys/dev/stge/
H A Dif_stge.c275 CSR_WRITE_1(sc, STGE_PhyCtrl, val);
995 CSR_WRITE_1(sc, STGE_WakeEvent, v);
1038 CSR_WRITE_1(sc, STGE_WakeEvent, v);
1961 CSR_WRITE_1(sc, STGE_PhySet, v);
2056 CSR_WRITE_1(sc, STGE_TxDMAPollPeriod, 127);
2059 CSR_WRITE_1(sc, STGE_RxDMAPollPeriod, 1);
2065 CSR_WRITE_1(sc, STGE_RxDMABurstThresh, 0x30);
2066 CSR_WRITE_1(sc, STGE_RxDMAUrgentThresh, 0x30);
2072 CSR_WRITE_1(sc, STGE_TxDMABurstThresh, 0x30);
2073 CSR_WRITE_1(s
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/freebsd-11-stable/sys/dev/iwi/
H A Dif_iwireg.h584 #define CSR_WRITE_1(sc, reg, val) \ macro
602 CSR_WRITE_1((sc), IWI_CSR_INDIRECT_DATA, (val)); \
/freebsd-11-stable/sys/dev/ale/
H A Dif_alevar.h233 #define CSR_WRITE_1(_sc, reg, val) \ macro
/freebsd-11-stable/sys/dev/alc/
H A Dif_alcvar.h263 #define CSR_WRITE_1(_sc, reg, val) \ macro
/freebsd-11-stable/sys/dev/xl/
H A Dif_xl.c469 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, macctl);
813 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX);
817 CSR_WRITE_1(sc, XL_W3_MAC_CTRL,
2108 CSR_WRITE_1(sc, XL_DOWN_POLL, 64);
2122 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8);
2145 CSR_WRITE_1(sc, XL_TX_STATUS, 0x01);
2717 CSR_WRITE_1(sc, XL_W2_STATION_ADDR_LO + i,
2758 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8);
2798 CSR_WRITE_1(sc, XL_DOWN_POLL, 64);
2831 CSR_WRITE_1(s
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