1/* $NetBSD: if_stge.c,v 1.32 2005/12/11 12:22:49 christos Exp $ */ 2 3/*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32/* 33 * Device driver for the Sundance Tech. TC9021 10/100/1000 34 * Ethernet controller. 35 */ 36 37#include <sys/cdefs.h> 38__FBSDID("$FreeBSD$"); 39 40#ifdef HAVE_KERNEL_OPTION_HEADERS 41#include "opt_device_polling.h" 42#endif 43 44#include <sys/param.h> 45#include <sys/systm.h> 46#include <sys/endian.h> 47#include <sys/mbuf.h> 48#include <sys/malloc.h> 49#include <sys/kernel.h> 50#include <sys/module.h> 51#include <sys/socket.h> 52#include <sys/sockio.h> 53#include <sys/sysctl.h> 54#include <sys/taskqueue.h> 55 56#include <net/bpf.h> 57#include <net/ethernet.h> 58#include <net/if.h> 59#include <net/if_var.h> 60#include <net/if_dl.h> 61#include <net/if_media.h> 62#include <net/if_types.h> 63#include <net/if_vlan_var.h> 64 65#include <machine/bus.h> 66#include <machine/resource.h> 67#include <sys/bus.h> 68#include <sys/rman.h> 69 70#include <dev/mii/mii.h> 71#include <dev/mii/mii_bitbang.h> 72#include <dev/mii/miivar.h> 73 74#include <dev/pci/pcireg.h> 75#include <dev/pci/pcivar.h> 76 77#include <dev/stge/if_stgereg.h> 78 79#define STGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 80 81MODULE_DEPEND(stge, pci, 1, 1, 1); 82MODULE_DEPEND(stge, ether, 1, 1, 1); 83MODULE_DEPEND(stge, miibus, 1, 1, 1); 84 85/* "device miibus" required. See GENERIC if you get errors here. */ 86#include "miibus_if.h" 87 88/* 89 * Devices supported by this driver. 90 */ 91static const struct stge_product { 92 uint16_t stge_vendorid; 93 uint16_t stge_deviceid; 94 const char *stge_name; 95} stge_products[] = { 96 { VENDOR_SUNDANCETI, DEVICEID_SUNDANCETI_ST1023, 97 "Sundance ST-1023 Gigabit Ethernet" }, 98 99 { VENDOR_SUNDANCETI, DEVICEID_SUNDANCETI_ST2021, 100 "Sundance ST-2021 Gigabit Ethernet" }, 101 102 { VENDOR_TAMARACK, DEVICEID_TAMARACK_TC9021, 103 "Tamarack TC9021 Gigabit Ethernet" }, 104 105 { VENDOR_TAMARACK, DEVICEID_TAMARACK_TC9021_ALT, 106 "Tamarack TC9021 Gigabit Ethernet" }, 107 108 /* 109 * The Sundance sample boards use the Sundance vendor ID, 110 * but the Tamarack product ID. 111 */ 112 { VENDOR_SUNDANCETI, DEVICEID_TAMARACK_TC9021, 113 "Sundance TC9021 Gigabit Ethernet" }, 114 115 { VENDOR_SUNDANCETI, DEVICEID_TAMARACK_TC9021_ALT, 116 "Sundance TC9021 Gigabit Ethernet" }, 117 118 { VENDOR_DLINK, DEVICEID_DLINK_DL4000, 119 "D-Link DL-4000 Gigabit Ethernet" }, 120 121 { VENDOR_ANTARES, DEVICEID_ANTARES_TC9021, 122 "Antares Gigabit Ethernet" } 123}; 124 125static int stge_probe(device_t); 126static int stge_attach(device_t); 127static int stge_detach(device_t); 128static int stge_shutdown(device_t); 129static int stge_suspend(device_t); 130static int stge_resume(device_t); 131 132static int stge_encap(struct stge_softc *, struct mbuf **); 133static void stge_start(struct ifnet *); 134static void stge_start_locked(struct ifnet *); 135static void stge_watchdog(struct stge_softc *); 136static int stge_ioctl(struct ifnet *, u_long, caddr_t); 137static void stge_init(void *); 138static void stge_init_locked(struct stge_softc *); 139static void stge_vlan_setup(struct stge_softc *); 140static void stge_stop(struct stge_softc *); 141static void stge_start_tx(struct stge_softc *); 142static void stge_start_rx(struct stge_softc *); 143static void stge_stop_tx(struct stge_softc *); 144static void stge_stop_rx(struct stge_softc *); 145 146static void stge_reset(struct stge_softc *, uint32_t); 147static int stge_eeprom_wait(struct stge_softc *); 148static void stge_read_eeprom(struct stge_softc *, int, uint16_t *); 149static void stge_tick(void *); 150static void stge_stats_update(struct stge_softc *); 151static void stge_set_filter(struct stge_softc *); 152static void stge_set_multi(struct stge_softc *); 153 154static void stge_link_task(void *, int); 155static void stge_intr(void *); 156static __inline int stge_tx_error(struct stge_softc *); 157static void stge_txeof(struct stge_softc *); 158static int stge_rxeof(struct stge_softc *); 159static __inline void stge_discard_rxbuf(struct stge_softc *, int); 160static int stge_newbuf(struct stge_softc *, int); 161#ifndef __NO_STRICT_ALIGNMENT 162static __inline struct mbuf *stge_fixup_rx(struct stge_softc *, struct mbuf *); 163#endif 164 165static int stge_miibus_readreg(device_t, int, int); 166static int stge_miibus_writereg(device_t, int, int, int); 167static void stge_miibus_statchg(device_t); 168static int stge_mediachange(struct ifnet *); 169static void stge_mediastatus(struct ifnet *, struct ifmediareq *); 170 171static void stge_dmamap_cb(void *, bus_dma_segment_t *, int, int); 172static int stge_dma_alloc(struct stge_softc *); 173static void stge_dma_free(struct stge_softc *); 174static void stge_dma_wait(struct stge_softc *); 175static void stge_init_tx_ring(struct stge_softc *); 176static int stge_init_rx_ring(struct stge_softc *); 177#ifdef DEVICE_POLLING 178static int stge_poll(struct ifnet *, enum poll_cmd, int); 179#endif 180 181static void stge_setwol(struct stge_softc *); 182static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 183static int sysctl_hw_stge_rxint_nframe(SYSCTL_HANDLER_ARGS); 184static int sysctl_hw_stge_rxint_dmawait(SYSCTL_HANDLER_ARGS); 185 186/* 187 * MII bit-bang glue 188 */ 189static uint32_t stge_mii_bitbang_read(device_t); 190static void stge_mii_bitbang_write(device_t, uint32_t); 191 192static const struct mii_bitbang_ops stge_mii_bitbang_ops = { 193 stge_mii_bitbang_read, 194 stge_mii_bitbang_write, 195 { 196 PC_MgmtData, /* MII_BIT_MDO */ 197 PC_MgmtData, /* MII_BIT_MDI */ 198 PC_MgmtClk, /* MII_BIT_MDC */ 199 PC_MgmtDir, /* MII_BIT_DIR_HOST_PHY */ 200 0, /* MII_BIT_DIR_PHY_HOST */ 201 } 202}; 203 204static device_method_t stge_methods[] = { 205 /* Device interface */ 206 DEVMETHOD(device_probe, stge_probe), 207 DEVMETHOD(device_attach, stge_attach), 208 DEVMETHOD(device_detach, stge_detach), 209 DEVMETHOD(device_shutdown, stge_shutdown), 210 DEVMETHOD(device_suspend, stge_suspend), 211 DEVMETHOD(device_resume, stge_resume), 212 213 /* MII interface */ 214 DEVMETHOD(miibus_readreg, stge_miibus_readreg), 215 DEVMETHOD(miibus_writereg, stge_miibus_writereg), 216 DEVMETHOD(miibus_statchg, stge_miibus_statchg), 217 218 DEVMETHOD_END 219}; 220 221static driver_t stge_driver = { 222 "stge", 223 stge_methods, 224 sizeof(struct stge_softc) 225}; 226 227static devclass_t stge_devclass; 228 229DRIVER_MODULE(stge, pci, stge_driver, stge_devclass, 0, 0); 230DRIVER_MODULE(miibus, stge, miibus_driver, miibus_devclass, 0, 0); 231 232static struct resource_spec stge_res_spec_io[] = { 233 { SYS_RES_IOPORT, PCIR_BAR(0), RF_ACTIVE }, 234 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 235 { -1, 0, 0 } 236}; 237 238static struct resource_spec stge_res_spec_mem[] = { 239 { SYS_RES_MEMORY, PCIR_BAR(1), RF_ACTIVE }, 240 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 241 { -1, 0, 0 } 242}; 243 244/* 245 * stge_mii_bitbang_read: [mii bit-bang interface function] 246 * 247 * Read the MII serial port for the MII bit-bang module. 248 */ 249static uint32_t 250stge_mii_bitbang_read(device_t dev) 251{ 252 struct stge_softc *sc; 253 uint32_t val; 254 255 sc = device_get_softc(dev); 256 257 val = CSR_READ_1(sc, STGE_PhyCtrl); 258 CSR_BARRIER(sc, STGE_PhyCtrl, 1, 259 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 260 return (val); 261} 262 263/* 264 * stge_mii_bitbang_write: [mii big-bang interface function] 265 * 266 * Write the MII serial port for the MII bit-bang module. 267 */ 268static void 269stge_mii_bitbang_write(device_t dev, uint32_t val) 270{ 271 struct stge_softc *sc; 272 273 sc = device_get_softc(dev); 274 275 CSR_WRITE_1(sc, STGE_PhyCtrl, val); 276 CSR_BARRIER(sc, STGE_PhyCtrl, 1, 277 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 278} 279 280/* 281 * sc_miibus_readreg: [mii interface function] 282 * 283 * Read a PHY register on the MII of the TC9021. 284 */ 285static int 286stge_miibus_readreg(device_t dev, int phy, int reg) 287{ 288 struct stge_softc *sc; 289 int error, val; 290 291 sc = device_get_softc(dev); 292 293 if (reg == STGE_PhyCtrl) { 294 /* XXX allow ip1000phy read STGE_PhyCtrl register. */ 295 STGE_MII_LOCK(sc); 296 error = CSR_READ_1(sc, STGE_PhyCtrl); 297 STGE_MII_UNLOCK(sc); 298 return (error); 299 } 300 301 STGE_MII_LOCK(sc); 302 val = mii_bitbang_readreg(dev, &stge_mii_bitbang_ops, phy, reg); 303 STGE_MII_UNLOCK(sc); 304 return (val); 305} 306 307/* 308 * stge_miibus_writereg: [mii interface function] 309 * 310 * Write a PHY register on the MII of the TC9021. 311 */ 312static int 313stge_miibus_writereg(device_t dev, int phy, int reg, int val) 314{ 315 struct stge_softc *sc; 316 317 sc = device_get_softc(dev); 318 319 STGE_MII_LOCK(sc); 320 mii_bitbang_writereg(dev, &stge_mii_bitbang_ops, phy, reg, val); 321 STGE_MII_UNLOCK(sc); 322 return (0); 323} 324 325/* 326 * stge_miibus_statchg: [mii interface function] 327 * 328 * Callback from MII layer when media changes. 329 */ 330static void 331stge_miibus_statchg(device_t dev) 332{ 333 struct stge_softc *sc; 334 335 sc = device_get_softc(dev); 336 taskqueue_enqueue(taskqueue_swi, &sc->sc_link_task); 337} 338 339/* 340 * stge_mediastatus: [ifmedia interface function] 341 * 342 * Get the current interface media status. 343 */ 344static void 345stge_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 346{ 347 struct stge_softc *sc; 348 struct mii_data *mii; 349 350 sc = ifp->if_softc; 351 mii = device_get_softc(sc->sc_miibus); 352 353 mii_pollstat(mii); 354 ifmr->ifm_status = mii->mii_media_status; 355 ifmr->ifm_active = mii->mii_media_active; 356} 357 358/* 359 * stge_mediachange: [ifmedia interface function] 360 * 361 * Set hardware to newly-selected media. 362 */ 363static int 364stge_mediachange(struct ifnet *ifp) 365{ 366 struct stge_softc *sc; 367 struct mii_data *mii; 368 369 sc = ifp->if_softc; 370 mii = device_get_softc(sc->sc_miibus); 371 mii_mediachg(mii); 372 373 return (0); 374} 375 376static int 377stge_eeprom_wait(struct stge_softc *sc) 378{ 379 int i; 380 381 for (i = 0; i < STGE_TIMEOUT; i++) { 382 DELAY(1000); 383 if ((CSR_READ_2(sc, STGE_EepromCtrl) & EC_EepromBusy) == 0) 384 return (0); 385 } 386 return (1); 387} 388 389/* 390 * stge_read_eeprom: 391 * 392 * Read data from the serial EEPROM. 393 */ 394static void 395stge_read_eeprom(struct stge_softc *sc, int offset, uint16_t *data) 396{ 397 398 if (stge_eeprom_wait(sc)) 399 device_printf(sc->sc_dev, "EEPROM failed to come ready\n"); 400 401 CSR_WRITE_2(sc, STGE_EepromCtrl, 402 EC_EepromAddress(offset) | EC_EepromOpcode(EC_OP_RR)); 403 if (stge_eeprom_wait(sc)) 404 device_printf(sc->sc_dev, "EEPROM read timed out\n"); 405 *data = CSR_READ_2(sc, STGE_EepromData); 406} 407 408 409static int 410stge_probe(device_t dev) 411{ 412 const struct stge_product *sp; 413 int i; 414 uint16_t vendor, devid; 415 416 vendor = pci_get_vendor(dev); 417 devid = pci_get_device(dev); 418 sp = stge_products; 419 for (i = 0; i < nitems(stge_products); i++, sp++) { 420 if (vendor == sp->stge_vendorid && 421 devid == sp->stge_deviceid) { 422 device_set_desc(dev, sp->stge_name); 423 return (BUS_PROBE_DEFAULT); 424 } 425 } 426 427 return (ENXIO); 428} 429 430static int 431stge_attach(device_t dev) 432{ 433 struct stge_softc *sc; 434 struct ifnet *ifp; 435 uint8_t enaddr[ETHER_ADDR_LEN]; 436 int error, flags, i; 437 uint16_t cmd; 438 uint32_t val; 439 440 error = 0; 441 sc = device_get_softc(dev); 442 sc->sc_dev = dev; 443 444 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 445 MTX_DEF); 446 mtx_init(&sc->sc_mii_mtx, "stge_mii_mutex", NULL, MTX_DEF); 447 callout_init_mtx(&sc->sc_tick_ch, &sc->sc_mtx, 0); 448 TASK_INIT(&sc->sc_link_task, 0, stge_link_task, sc); 449 450 /* 451 * Map the device. 452 */ 453 pci_enable_busmaster(dev); 454 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 455 val = pci_read_config(dev, PCIR_BAR(1), 4); 456 if (PCI_BAR_IO(val)) 457 sc->sc_spec = stge_res_spec_mem; 458 else { 459 val = pci_read_config(dev, PCIR_BAR(0), 4); 460 if (!PCI_BAR_IO(val)) { 461 device_printf(sc->sc_dev, "couldn't locate IO BAR\n"); 462 error = ENXIO; 463 goto fail; 464 } 465 sc->sc_spec = stge_res_spec_io; 466 } 467 error = bus_alloc_resources(dev, sc->sc_spec, sc->sc_res); 468 if (error != 0) { 469 device_printf(dev, "couldn't allocate %s resources\n", 470 sc->sc_spec == stge_res_spec_mem ? "memory" : "I/O"); 471 goto fail; 472 } 473 sc->sc_rev = pci_get_revid(dev); 474 475 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 476 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 477 "rxint_nframe", CTLTYPE_INT|CTLFLAG_RW, &sc->sc_rxint_nframe, 0, 478 sysctl_hw_stge_rxint_nframe, "I", "stge rx interrupt nframe"); 479 480 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 481 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 482 "rxint_dmawait", CTLTYPE_INT|CTLFLAG_RW, &sc->sc_rxint_dmawait, 0, 483 sysctl_hw_stge_rxint_dmawait, "I", "stge rx interrupt dmawait"); 484 485 /* Pull in device tunables. */ 486 sc->sc_rxint_nframe = STGE_RXINT_NFRAME_DEFAULT; 487 error = resource_int_value(device_get_name(dev), device_get_unit(dev), 488 "rxint_nframe", &sc->sc_rxint_nframe); 489 if (error == 0) { 490 if (sc->sc_rxint_nframe < STGE_RXINT_NFRAME_MIN || 491 sc->sc_rxint_nframe > STGE_RXINT_NFRAME_MAX) { 492 device_printf(dev, "rxint_nframe value out of range; " 493 "using default: %d\n", STGE_RXINT_NFRAME_DEFAULT); 494 sc->sc_rxint_nframe = STGE_RXINT_NFRAME_DEFAULT; 495 } 496 } 497 498 sc->sc_rxint_dmawait = STGE_RXINT_DMAWAIT_DEFAULT; 499 error = resource_int_value(device_get_name(dev), device_get_unit(dev), 500 "rxint_dmawait", &sc->sc_rxint_dmawait); 501 if (error == 0) { 502 if (sc->sc_rxint_dmawait < STGE_RXINT_DMAWAIT_MIN || 503 sc->sc_rxint_dmawait > STGE_RXINT_DMAWAIT_MAX) { 504 device_printf(dev, "rxint_dmawait value out of range; " 505 "using default: %d\n", STGE_RXINT_DMAWAIT_DEFAULT); 506 sc->sc_rxint_dmawait = STGE_RXINT_DMAWAIT_DEFAULT; 507 } 508 } 509 510 if ((error = stge_dma_alloc(sc)) != 0) 511 goto fail; 512 513 /* 514 * Determine if we're copper or fiber. It affects how we 515 * reset the card. 516 */ 517 if (CSR_READ_4(sc, STGE_AsicCtrl) & AC_PhyMedia) 518 sc->sc_usefiber = 1; 519 else 520 sc->sc_usefiber = 0; 521 522 /* Load LED configuration from EEPROM. */ 523 stge_read_eeprom(sc, STGE_EEPROM_LEDMode, &sc->sc_led); 524 525 /* 526 * Reset the chip to a known state. 527 */ 528 STGE_LOCK(sc); 529 stge_reset(sc, STGE_RESET_FULL); 530 STGE_UNLOCK(sc); 531 532 /* 533 * Reading the station address from the EEPROM doesn't seem 534 * to work, at least on my sample boards. Instead, since 535 * the reset sequence does AutoInit, read it from the station 536 * address registers. For Sundance 1023 you can only read it 537 * from EEPROM. 538 */ 539 if (pci_get_device(dev) != DEVICEID_SUNDANCETI_ST1023) { 540 uint16_t v; 541 542 v = CSR_READ_2(sc, STGE_StationAddress0); 543 enaddr[0] = v & 0xff; 544 enaddr[1] = v >> 8; 545 v = CSR_READ_2(sc, STGE_StationAddress1); 546 enaddr[2] = v & 0xff; 547 enaddr[3] = v >> 8; 548 v = CSR_READ_2(sc, STGE_StationAddress2); 549 enaddr[4] = v & 0xff; 550 enaddr[5] = v >> 8; 551 sc->sc_stge1023 = 0; 552 } else { 553 uint16_t myaddr[ETHER_ADDR_LEN / 2]; 554 for (i = 0; i <ETHER_ADDR_LEN / 2; i++) { 555 stge_read_eeprom(sc, STGE_EEPROM_StationAddress0 + i, 556 &myaddr[i]); 557 myaddr[i] = le16toh(myaddr[i]); 558 } 559 bcopy(myaddr, enaddr, sizeof(enaddr)); 560 sc->sc_stge1023 = 1; 561 } 562 563 ifp = sc->sc_ifp = if_alloc(IFT_ETHER); 564 if (ifp == NULL) { 565 device_printf(sc->sc_dev, "failed to if_alloc()\n"); 566 error = ENXIO; 567 goto fail; 568 } 569 570 ifp->if_softc = sc; 571 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 572 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 573 ifp->if_ioctl = stge_ioctl; 574 ifp->if_start = stge_start; 575 ifp->if_init = stge_init; 576 ifp->if_snd.ifq_drv_maxlen = STGE_TX_RING_CNT - 1; 577 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 578 IFQ_SET_READY(&ifp->if_snd); 579 /* Revision B3 and earlier chips have checksum bug. */ 580 if (sc->sc_rev >= 0x0c) { 581 ifp->if_hwassist = STGE_CSUM_FEATURES; 582 ifp->if_capabilities = IFCAP_HWCSUM; 583 } else { 584 ifp->if_hwassist = 0; 585 ifp->if_capabilities = 0; 586 } 587 ifp->if_capabilities |= IFCAP_WOL_MAGIC; 588 ifp->if_capenable = ifp->if_capabilities; 589 590 /* 591 * Read some important bits from the PhyCtrl register. 592 */ 593 sc->sc_PhyCtrl = CSR_READ_1(sc, STGE_PhyCtrl) & 594 (PC_PhyDuplexPolarity | PC_PhyLnkPolarity); 595 596 /* Set up MII bus. */ 597 flags = MIIF_DOPAUSE; 598 if (sc->sc_rev >= 0x40 && sc->sc_rev <= 0x4e) 599 flags |= MIIF_MACPRIV0; 600 error = mii_attach(sc->sc_dev, &sc->sc_miibus, ifp, stge_mediachange, 601 stge_mediastatus, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 602 flags); 603 if (error != 0) { 604 device_printf(sc->sc_dev, "attaching PHYs failed\n"); 605 goto fail; 606 } 607 608 ether_ifattach(ifp, enaddr); 609 610 /* VLAN capability setup */ 611 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; 612 if (sc->sc_rev >= 0x0c) 613 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 614 ifp->if_capenable = ifp->if_capabilities; 615#ifdef DEVICE_POLLING 616 ifp->if_capabilities |= IFCAP_POLLING; 617#endif 618 /* 619 * Tell the upper layer(s) we support long frames. 620 * Must appear after the call to ether_ifattach() because 621 * ether_ifattach() sets ifi_hdrlen to the default value. 622 */ 623 ifp->if_hdrlen = sizeof(struct ether_vlan_header); 624 625 /* 626 * The manual recommends disabling early transmit, so we 627 * do. It's disabled anyway, if using IP checksumming, 628 * since the entire packet must be in the FIFO in order 629 * for the chip to perform the checksum. 630 */ 631 sc->sc_txthresh = 0x0fff; 632 633 /* 634 * Disable MWI if the PCI layer tells us to. 635 */ 636 sc->sc_DMACtrl = 0; 637 if ((cmd & PCIM_CMD_MWRICEN) == 0) 638 sc->sc_DMACtrl |= DMAC_MWIDisable; 639 640 /* 641 * Hookup IRQ 642 */ 643 error = bus_setup_intr(dev, sc->sc_res[1], INTR_TYPE_NET | INTR_MPSAFE, 644 NULL, stge_intr, sc, &sc->sc_ih); 645 if (error != 0) { 646 ether_ifdetach(ifp); 647 device_printf(sc->sc_dev, "couldn't set up IRQ\n"); 648 sc->sc_ifp = NULL; 649 goto fail; 650 } 651 652fail: 653 if (error != 0) 654 stge_detach(dev); 655 656 return (error); 657} 658 659static int 660stge_detach(device_t dev) 661{ 662 struct stge_softc *sc; 663 struct ifnet *ifp; 664 665 sc = device_get_softc(dev); 666 667 ifp = sc->sc_ifp; 668#ifdef DEVICE_POLLING 669 if (ifp && ifp->if_capenable & IFCAP_POLLING) 670 ether_poll_deregister(ifp); 671#endif 672 if (device_is_attached(dev)) { 673 STGE_LOCK(sc); 674 /* XXX */ 675 sc->sc_detach = 1; 676 stge_stop(sc); 677 STGE_UNLOCK(sc); 678 callout_drain(&sc->sc_tick_ch); 679 taskqueue_drain(taskqueue_swi, &sc->sc_link_task); 680 ether_ifdetach(ifp); 681 } 682 683 if (sc->sc_miibus != NULL) { 684 device_delete_child(dev, sc->sc_miibus); 685 sc->sc_miibus = NULL; 686 } 687 bus_generic_detach(dev); 688 stge_dma_free(sc); 689 690 if (ifp != NULL) { 691 if_free(ifp); 692 sc->sc_ifp = NULL; 693 } 694 695 if (sc->sc_ih) { 696 bus_teardown_intr(dev, sc->sc_res[1], sc->sc_ih); 697 sc->sc_ih = NULL; 698 } 699 bus_release_resources(dev, sc->sc_spec, sc->sc_res); 700 701 mtx_destroy(&sc->sc_mii_mtx); 702 mtx_destroy(&sc->sc_mtx); 703 704 return (0); 705} 706 707struct stge_dmamap_arg { 708 bus_addr_t stge_busaddr; 709}; 710 711static void 712stge_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 713{ 714 struct stge_dmamap_arg *ctx; 715 716 if (error != 0) 717 return; 718 719 ctx = (struct stge_dmamap_arg *)arg; 720 ctx->stge_busaddr = segs[0].ds_addr; 721} 722 723static int 724stge_dma_alloc(struct stge_softc *sc) 725{ 726 struct stge_dmamap_arg ctx; 727 struct stge_txdesc *txd; 728 struct stge_rxdesc *rxd; 729 int error, i; 730 731 /* create parent tag. */ 732 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev),/* parent */ 733 1, 0, /* algnmnt, boundary */ 734 STGE_DMA_MAXADDR, /* lowaddr */ 735 BUS_SPACE_MAXADDR, /* highaddr */ 736 NULL, NULL, /* filter, filterarg */ 737 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 738 0, /* nsegments */ 739 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 740 0, /* flags */ 741 NULL, NULL, /* lockfunc, lockarg */ 742 &sc->sc_cdata.stge_parent_tag); 743 if (error != 0) { 744 device_printf(sc->sc_dev, "failed to create parent DMA tag\n"); 745 goto fail; 746 } 747 /* create tag for Tx ring. */ 748 error = bus_dma_tag_create(sc->sc_cdata.stge_parent_tag,/* parent */ 749 STGE_RING_ALIGN, 0, /* algnmnt, boundary */ 750 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 751 BUS_SPACE_MAXADDR, /* highaddr */ 752 NULL, NULL, /* filter, filterarg */ 753 STGE_TX_RING_SZ, /* maxsize */ 754 1, /* nsegments */ 755 STGE_TX_RING_SZ, /* maxsegsize */ 756 0, /* flags */ 757 NULL, NULL, /* lockfunc, lockarg */ 758 &sc->sc_cdata.stge_tx_ring_tag); 759 if (error != 0) { 760 device_printf(sc->sc_dev, 761 "failed to allocate Tx ring DMA tag\n"); 762 goto fail; 763 } 764 765 /* create tag for Rx ring. */ 766 error = bus_dma_tag_create(sc->sc_cdata.stge_parent_tag,/* parent */ 767 STGE_RING_ALIGN, 0, /* algnmnt, boundary */ 768 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 769 BUS_SPACE_MAXADDR, /* highaddr */ 770 NULL, NULL, /* filter, filterarg */ 771 STGE_RX_RING_SZ, /* maxsize */ 772 1, /* nsegments */ 773 STGE_RX_RING_SZ, /* maxsegsize */ 774 0, /* flags */ 775 NULL, NULL, /* lockfunc, lockarg */ 776 &sc->sc_cdata.stge_rx_ring_tag); 777 if (error != 0) { 778 device_printf(sc->sc_dev, 779 "failed to allocate Rx ring DMA tag\n"); 780 goto fail; 781 } 782 783 /* create tag for Tx buffers. */ 784 error = bus_dma_tag_create(sc->sc_cdata.stge_parent_tag,/* parent */ 785 1, 0, /* algnmnt, boundary */ 786 BUS_SPACE_MAXADDR, /* lowaddr */ 787 BUS_SPACE_MAXADDR, /* highaddr */ 788 NULL, NULL, /* filter, filterarg */ 789 MCLBYTES * STGE_MAXTXSEGS, /* maxsize */ 790 STGE_MAXTXSEGS, /* nsegments */ 791 MCLBYTES, /* maxsegsize */ 792 0, /* flags */ 793 NULL, NULL, /* lockfunc, lockarg */ 794 &sc->sc_cdata.stge_tx_tag); 795 if (error != 0) { 796 device_printf(sc->sc_dev, "failed to allocate Tx DMA tag\n"); 797 goto fail; 798 } 799 800 /* create tag for Rx buffers. */ 801 error = bus_dma_tag_create(sc->sc_cdata.stge_parent_tag,/* parent */ 802 1, 0, /* algnmnt, boundary */ 803 BUS_SPACE_MAXADDR, /* lowaddr */ 804 BUS_SPACE_MAXADDR, /* highaddr */ 805 NULL, NULL, /* filter, filterarg */ 806 MCLBYTES, /* maxsize */ 807 1, /* nsegments */ 808 MCLBYTES, /* maxsegsize */ 809 0, /* flags */ 810 NULL, NULL, /* lockfunc, lockarg */ 811 &sc->sc_cdata.stge_rx_tag); 812 if (error != 0) { 813 device_printf(sc->sc_dev, "failed to allocate Rx DMA tag\n"); 814 goto fail; 815 } 816 817 /* allocate DMA'able memory and load the DMA map for Tx ring. */ 818 error = bus_dmamem_alloc(sc->sc_cdata.stge_tx_ring_tag, 819 (void **)&sc->sc_rdata.stge_tx_ring, BUS_DMA_NOWAIT | 820 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->sc_cdata.stge_tx_ring_map); 821 if (error != 0) { 822 device_printf(sc->sc_dev, 823 "failed to allocate DMA'able memory for Tx ring\n"); 824 goto fail; 825 } 826 827 ctx.stge_busaddr = 0; 828 error = bus_dmamap_load(sc->sc_cdata.stge_tx_ring_tag, 829 sc->sc_cdata.stge_tx_ring_map, sc->sc_rdata.stge_tx_ring, 830 STGE_TX_RING_SZ, stge_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 831 if (error != 0 || ctx.stge_busaddr == 0) { 832 device_printf(sc->sc_dev, 833 "failed to load DMA'able memory for Tx ring\n"); 834 goto fail; 835 } 836 sc->sc_rdata.stge_tx_ring_paddr = ctx.stge_busaddr; 837 838 /* allocate DMA'able memory and load the DMA map for Rx ring. */ 839 error = bus_dmamem_alloc(sc->sc_cdata.stge_rx_ring_tag, 840 (void **)&sc->sc_rdata.stge_rx_ring, BUS_DMA_NOWAIT | 841 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->sc_cdata.stge_rx_ring_map); 842 if (error != 0) { 843 device_printf(sc->sc_dev, 844 "failed to allocate DMA'able memory for Rx ring\n"); 845 goto fail; 846 } 847 848 ctx.stge_busaddr = 0; 849 error = bus_dmamap_load(sc->sc_cdata.stge_rx_ring_tag, 850 sc->sc_cdata.stge_rx_ring_map, sc->sc_rdata.stge_rx_ring, 851 STGE_RX_RING_SZ, stge_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 852 if (error != 0 || ctx.stge_busaddr == 0) { 853 device_printf(sc->sc_dev, 854 "failed to load DMA'able memory for Rx ring\n"); 855 goto fail; 856 } 857 sc->sc_rdata.stge_rx_ring_paddr = ctx.stge_busaddr; 858 859 /* create DMA maps for Tx buffers. */ 860 for (i = 0; i < STGE_TX_RING_CNT; i++) { 861 txd = &sc->sc_cdata.stge_txdesc[i]; 862 txd->tx_m = NULL; 863 txd->tx_dmamap = 0; 864 error = bus_dmamap_create(sc->sc_cdata.stge_tx_tag, 0, 865 &txd->tx_dmamap); 866 if (error != 0) { 867 device_printf(sc->sc_dev, 868 "failed to create Tx dmamap\n"); 869 goto fail; 870 } 871 } 872 /* create DMA maps for Rx buffers. */ 873 if ((error = bus_dmamap_create(sc->sc_cdata.stge_rx_tag, 0, 874 &sc->sc_cdata.stge_rx_sparemap)) != 0) { 875 device_printf(sc->sc_dev, "failed to create spare Rx dmamap\n"); 876 goto fail; 877 } 878 for (i = 0; i < STGE_RX_RING_CNT; i++) { 879 rxd = &sc->sc_cdata.stge_rxdesc[i]; 880 rxd->rx_m = NULL; 881 rxd->rx_dmamap = 0; 882 error = bus_dmamap_create(sc->sc_cdata.stge_rx_tag, 0, 883 &rxd->rx_dmamap); 884 if (error != 0) { 885 device_printf(sc->sc_dev, 886 "failed to create Rx dmamap\n"); 887 goto fail; 888 } 889 } 890 891fail: 892 return (error); 893} 894 895static void 896stge_dma_free(struct stge_softc *sc) 897{ 898 struct stge_txdesc *txd; 899 struct stge_rxdesc *rxd; 900 int i; 901 902 /* Tx ring */ 903 if (sc->sc_cdata.stge_tx_ring_tag) { 904 if (sc->sc_rdata.stge_tx_ring_paddr) 905 bus_dmamap_unload(sc->sc_cdata.stge_tx_ring_tag, 906 sc->sc_cdata.stge_tx_ring_map); 907 if (sc->sc_rdata.stge_tx_ring) 908 bus_dmamem_free(sc->sc_cdata.stge_tx_ring_tag, 909 sc->sc_rdata.stge_tx_ring, 910 sc->sc_cdata.stge_tx_ring_map); 911 sc->sc_rdata.stge_tx_ring = NULL; 912 sc->sc_rdata.stge_tx_ring_paddr = 0; 913 bus_dma_tag_destroy(sc->sc_cdata.stge_tx_ring_tag); 914 sc->sc_cdata.stge_tx_ring_tag = NULL; 915 } 916 /* Rx ring */ 917 if (sc->sc_cdata.stge_rx_ring_tag) { 918 if (sc->sc_rdata.stge_rx_ring_paddr) 919 bus_dmamap_unload(sc->sc_cdata.stge_rx_ring_tag, 920 sc->sc_cdata.stge_rx_ring_map); 921 if (sc->sc_rdata.stge_rx_ring) 922 bus_dmamem_free(sc->sc_cdata.stge_rx_ring_tag, 923 sc->sc_rdata.stge_rx_ring, 924 sc->sc_cdata.stge_rx_ring_map); 925 sc->sc_rdata.stge_rx_ring = NULL; 926 sc->sc_rdata.stge_rx_ring_paddr = 0; 927 bus_dma_tag_destroy(sc->sc_cdata.stge_rx_ring_tag); 928 sc->sc_cdata.stge_rx_ring_tag = NULL; 929 } 930 /* Tx buffers */ 931 if (sc->sc_cdata.stge_tx_tag) { 932 for (i = 0; i < STGE_TX_RING_CNT; i++) { 933 txd = &sc->sc_cdata.stge_txdesc[i]; 934 if (txd->tx_dmamap) { 935 bus_dmamap_destroy(sc->sc_cdata.stge_tx_tag, 936 txd->tx_dmamap); 937 txd->tx_dmamap = 0; 938 } 939 } 940 bus_dma_tag_destroy(sc->sc_cdata.stge_tx_tag); 941 sc->sc_cdata.stge_tx_tag = NULL; 942 } 943 /* Rx buffers */ 944 if (sc->sc_cdata.stge_rx_tag) { 945 for (i = 0; i < STGE_RX_RING_CNT; i++) { 946 rxd = &sc->sc_cdata.stge_rxdesc[i]; 947 if (rxd->rx_dmamap) { 948 bus_dmamap_destroy(sc->sc_cdata.stge_rx_tag, 949 rxd->rx_dmamap); 950 rxd->rx_dmamap = 0; 951 } 952 } 953 if (sc->sc_cdata.stge_rx_sparemap) { 954 bus_dmamap_destroy(sc->sc_cdata.stge_rx_tag, 955 sc->sc_cdata.stge_rx_sparemap); 956 sc->sc_cdata.stge_rx_sparemap = 0; 957 } 958 bus_dma_tag_destroy(sc->sc_cdata.stge_rx_tag); 959 sc->sc_cdata.stge_rx_tag = NULL; 960 } 961 962 if (sc->sc_cdata.stge_parent_tag) { 963 bus_dma_tag_destroy(sc->sc_cdata.stge_parent_tag); 964 sc->sc_cdata.stge_parent_tag = NULL; 965 } 966} 967 968/* 969 * stge_shutdown: 970 * 971 * Make sure the interface is stopped at reboot time. 972 */ 973static int 974stge_shutdown(device_t dev) 975{ 976 977 return (stge_suspend(dev)); 978} 979 980static void 981stge_setwol(struct stge_softc *sc) 982{ 983 struct ifnet *ifp; 984 uint8_t v; 985 986 STGE_LOCK_ASSERT(sc); 987 988 ifp = sc->sc_ifp; 989 v = CSR_READ_1(sc, STGE_WakeEvent); 990 /* Disable all WOL bits. */ 991 v &= ~(WE_WakePktEnable | WE_MagicPktEnable | WE_LinkEventEnable | 992 WE_WakeOnLanEnable); 993 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 994 v |= WE_MagicPktEnable | WE_WakeOnLanEnable; 995 CSR_WRITE_1(sc, STGE_WakeEvent, v); 996 /* Reset Tx and prevent transmission. */ 997 CSR_WRITE_4(sc, STGE_AsicCtrl, 998 CSR_READ_4(sc, STGE_AsicCtrl) | AC_TxReset); 999 /* 1000 * TC9021 automatically reset link speed to 100Mbps when it's put 1001 * into sleep so there is no need to try to resetting link speed. 1002 */ 1003} 1004 1005static int 1006stge_suspend(device_t dev) 1007{ 1008 struct stge_softc *sc; 1009 1010 sc = device_get_softc(dev); 1011 1012 STGE_LOCK(sc); 1013 stge_stop(sc); 1014 sc->sc_suspended = 1; 1015 stge_setwol(sc); 1016 STGE_UNLOCK(sc); 1017 1018 return (0); 1019} 1020 1021static int 1022stge_resume(device_t dev) 1023{ 1024 struct stge_softc *sc; 1025 struct ifnet *ifp; 1026 uint8_t v; 1027 1028 sc = device_get_softc(dev); 1029 1030 STGE_LOCK(sc); 1031 /* 1032 * Clear WOL bits, so special frames wouldn't interfere 1033 * normal Rx operation anymore. 1034 */ 1035 v = CSR_READ_1(sc, STGE_WakeEvent); 1036 v &= ~(WE_WakePktEnable | WE_MagicPktEnable | WE_LinkEventEnable | 1037 WE_WakeOnLanEnable); 1038 CSR_WRITE_1(sc, STGE_WakeEvent, v); 1039 ifp = sc->sc_ifp; 1040 if (ifp->if_flags & IFF_UP) 1041 stge_init_locked(sc); 1042 1043 sc->sc_suspended = 0; 1044 STGE_UNLOCK(sc); 1045 1046 return (0); 1047} 1048 1049static void 1050stge_dma_wait(struct stge_softc *sc) 1051{ 1052 int i; 1053 1054 for (i = 0; i < STGE_TIMEOUT; i++) { 1055 DELAY(2); 1056 if ((CSR_READ_4(sc, STGE_DMACtrl) & DMAC_TxDMAInProg) == 0) 1057 break; 1058 } 1059 1060 if (i == STGE_TIMEOUT) 1061 device_printf(sc->sc_dev, "DMA wait timed out\n"); 1062} 1063 1064static int 1065stge_encap(struct stge_softc *sc, struct mbuf **m_head) 1066{ 1067 struct stge_txdesc *txd; 1068 struct stge_tfd *tfd; 1069 struct mbuf *m; 1070 bus_dma_segment_t txsegs[STGE_MAXTXSEGS]; 1071 int error, i, nsegs, si; 1072 uint64_t csum_flags, tfc; 1073 1074 STGE_LOCK_ASSERT(sc); 1075 1076 if ((txd = STAILQ_FIRST(&sc->sc_cdata.stge_txfreeq)) == NULL) 1077 return (ENOBUFS); 1078 1079 error = bus_dmamap_load_mbuf_sg(sc->sc_cdata.stge_tx_tag, 1080 txd->tx_dmamap, *m_head, txsegs, &nsegs, 0); 1081 if (error == EFBIG) { 1082 m = m_collapse(*m_head, M_NOWAIT, STGE_MAXTXSEGS); 1083 if (m == NULL) { 1084 m_freem(*m_head); 1085 *m_head = NULL; 1086 return (ENOMEM); 1087 } 1088 *m_head = m; 1089 error = bus_dmamap_load_mbuf_sg(sc->sc_cdata.stge_tx_tag, 1090 txd->tx_dmamap, *m_head, txsegs, &nsegs, 0); 1091 if (error != 0) { 1092 m_freem(*m_head); 1093 *m_head = NULL; 1094 return (error); 1095 } 1096 } else if (error != 0) 1097 return (error); 1098 if (nsegs == 0) { 1099 m_freem(*m_head); 1100 *m_head = NULL; 1101 return (EIO); 1102 } 1103 1104 m = *m_head; 1105 csum_flags = 0; 1106 if ((m->m_pkthdr.csum_flags & STGE_CSUM_FEATURES) != 0) { 1107 if (m->m_pkthdr.csum_flags & CSUM_IP) 1108 csum_flags |= TFD_IPChecksumEnable; 1109 if (m->m_pkthdr.csum_flags & CSUM_TCP) 1110 csum_flags |= TFD_TCPChecksumEnable; 1111 else if (m->m_pkthdr.csum_flags & CSUM_UDP) 1112 csum_flags |= TFD_UDPChecksumEnable; 1113 } 1114 1115 si = sc->sc_cdata.stge_tx_prod; 1116 tfd = &sc->sc_rdata.stge_tx_ring[si]; 1117 for (i = 0; i < nsegs; i++) 1118 tfd->tfd_frags[i].frag_word0 = 1119 htole64(FRAG_ADDR(txsegs[i].ds_addr) | 1120 FRAG_LEN(txsegs[i].ds_len)); 1121 sc->sc_cdata.stge_tx_cnt++; 1122 1123 tfc = TFD_FrameId(si) | TFD_WordAlign(TFD_WordAlign_disable) | 1124 TFD_FragCount(nsegs) | csum_flags; 1125 if (sc->sc_cdata.stge_tx_cnt >= STGE_TX_HIWAT) 1126 tfc |= TFD_TxDMAIndicate; 1127 1128 /* Update producer index. */ 1129 sc->sc_cdata.stge_tx_prod = (si + 1) % STGE_TX_RING_CNT; 1130 1131 /* Check if we have a VLAN tag to insert. */ 1132 if (m->m_flags & M_VLANTAG) 1133 tfc |= (TFD_VLANTagInsert | TFD_VID(m->m_pkthdr.ether_vtag)); 1134 tfd->tfd_control = htole64(tfc); 1135 1136 /* Update Tx Queue. */ 1137 STAILQ_REMOVE_HEAD(&sc->sc_cdata.stge_txfreeq, tx_q); 1138 STAILQ_INSERT_TAIL(&sc->sc_cdata.stge_txbusyq, txd, tx_q); 1139 txd->tx_m = m; 1140 1141 /* Sync descriptors. */ 1142 bus_dmamap_sync(sc->sc_cdata.stge_tx_tag, txd->tx_dmamap, 1143 BUS_DMASYNC_PREWRITE); 1144 bus_dmamap_sync(sc->sc_cdata.stge_tx_ring_tag, 1145 sc->sc_cdata.stge_tx_ring_map, 1146 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1147 1148 return (0); 1149} 1150 1151/* 1152 * stge_start: [ifnet interface function] 1153 * 1154 * Start packet transmission on the interface. 1155 */ 1156static void 1157stge_start(struct ifnet *ifp) 1158{ 1159 struct stge_softc *sc; 1160 1161 sc = ifp->if_softc; 1162 STGE_LOCK(sc); 1163 stge_start_locked(ifp); 1164 STGE_UNLOCK(sc); 1165} 1166 1167static void 1168stge_start_locked(struct ifnet *ifp) 1169{ 1170 struct stge_softc *sc; 1171 struct mbuf *m_head; 1172 int enq; 1173 1174 sc = ifp->if_softc; 1175 1176 STGE_LOCK_ASSERT(sc); 1177 1178 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING|IFF_DRV_OACTIVE)) != 1179 IFF_DRV_RUNNING || sc->sc_link == 0) 1180 return; 1181 1182 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) { 1183 if (sc->sc_cdata.stge_tx_cnt >= STGE_TX_HIWAT) { 1184 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1185 break; 1186 } 1187 1188 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1189 if (m_head == NULL) 1190 break; 1191 /* 1192 * Pack the data into the transmit ring. If we 1193 * don't have room, set the OACTIVE flag and wait 1194 * for the NIC to drain the ring. 1195 */ 1196 if (stge_encap(sc, &m_head)) { 1197 if (m_head == NULL) 1198 break; 1199 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1200 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1201 break; 1202 } 1203 1204 enq++; 1205 /* 1206 * If there's a BPF listener, bounce a copy of this frame 1207 * to him. 1208 */ 1209 ETHER_BPF_MTAP(ifp, m_head); 1210 } 1211 1212 if (enq > 0) { 1213 /* Transmit */ 1214 CSR_WRITE_4(sc, STGE_DMACtrl, DMAC_TxDMAPollNow); 1215 1216 /* Set a timeout in case the chip goes out to lunch. */ 1217 sc->sc_watchdog_timer = 5; 1218 } 1219} 1220 1221/* 1222 * stge_watchdog: 1223 * 1224 * Watchdog timer handler. 1225 */ 1226static void 1227stge_watchdog(struct stge_softc *sc) 1228{ 1229 struct ifnet *ifp; 1230 1231 STGE_LOCK_ASSERT(sc); 1232 1233 if (sc->sc_watchdog_timer == 0 || --sc->sc_watchdog_timer) 1234 return; 1235 1236 ifp = sc->sc_ifp; 1237 if_printf(sc->sc_ifp, "device timeout\n"); 1238 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1239 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1240 stge_init_locked(sc); 1241 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1242 stge_start_locked(ifp); 1243} 1244 1245/* 1246 * stge_ioctl: [ifnet interface function] 1247 * 1248 * Handle control requests from the operator. 1249 */ 1250static int 1251stge_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1252{ 1253 struct stge_softc *sc; 1254 struct ifreq *ifr; 1255 struct mii_data *mii; 1256 int error, mask; 1257 1258 sc = ifp->if_softc; 1259 ifr = (struct ifreq *)data; 1260 error = 0; 1261 switch (cmd) { 1262 case SIOCSIFMTU: 1263 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > STGE_JUMBO_MTU) 1264 error = EINVAL; 1265 else if (ifp->if_mtu != ifr->ifr_mtu) { 1266 ifp->if_mtu = ifr->ifr_mtu; 1267 STGE_LOCK(sc); 1268 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1269 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1270 stge_init_locked(sc); 1271 } 1272 STGE_UNLOCK(sc); 1273 } 1274 break; 1275 case SIOCSIFFLAGS: 1276 STGE_LOCK(sc); 1277 if ((ifp->if_flags & IFF_UP) != 0) { 1278 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1279 if (((ifp->if_flags ^ sc->sc_if_flags) 1280 & IFF_PROMISC) != 0) 1281 stge_set_filter(sc); 1282 } else { 1283 if (sc->sc_detach == 0) 1284 stge_init_locked(sc); 1285 } 1286 } else { 1287 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1288 stge_stop(sc); 1289 } 1290 sc->sc_if_flags = ifp->if_flags; 1291 STGE_UNLOCK(sc); 1292 break; 1293 case SIOCADDMULTI: 1294 case SIOCDELMULTI: 1295 STGE_LOCK(sc); 1296 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1297 stge_set_multi(sc); 1298 STGE_UNLOCK(sc); 1299 break; 1300 case SIOCSIFMEDIA: 1301 case SIOCGIFMEDIA: 1302 mii = device_get_softc(sc->sc_miibus); 1303 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1304 break; 1305 case SIOCSIFCAP: 1306 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1307#ifdef DEVICE_POLLING 1308 if ((mask & IFCAP_POLLING) != 0) { 1309 if ((ifr->ifr_reqcap & IFCAP_POLLING) != 0) { 1310 error = ether_poll_register(stge_poll, ifp); 1311 if (error != 0) 1312 break; 1313 STGE_LOCK(sc); 1314 CSR_WRITE_2(sc, STGE_IntEnable, 0); 1315 ifp->if_capenable |= IFCAP_POLLING; 1316 STGE_UNLOCK(sc); 1317 } else { 1318 error = ether_poll_deregister(ifp); 1319 if (error != 0) 1320 break; 1321 STGE_LOCK(sc); 1322 CSR_WRITE_2(sc, STGE_IntEnable, 1323 sc->sc_IntEnable); 1324 ifp->if_capenable &= ~IFCAP_POLLING; 1325 STGE_UNLOCK(sc); 1326 } 1327 } 1328#endif 1329 if ((mask & IFCAP_HWCSUM) != 0) { 1330 ifp->if_capenable ^= IFCAP_HWCSUM; 1331 if ((IFCAP_HWCSUM & ifp->if_capenable) != 0 && 1332 (IFCAP_HWCSUM & ifp->if_capabilities) != 0) 1333 ifp->if_hwassist = STGE_CSUM_FEATURES; 1334 else 1335 ifp->if_hwassist = 0; 1336 } 1337 if ((mask & IFCAP_WOL) != 0 && 1338 (ifp->if_capabilities & IFCAP_WOL) != 0) { 1339 if ((mask & IFCAP_WOL_MAGIC) != 0) 1340 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 1341 } 1342 if ((mask & IFCAP_VLAN_HWTAGGING) != 0) { 1343 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 1344 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1345 STGE_LOCK(sc); 1346 stge_vlan_setup(sc); 1347 STGE_UNLOCK(sc); 1348 } 1349 } 1350 VLAN_CAPABILITIES(ifp); 1351 break; 1352 default: 1353 error = ether_ioctl(ifp, cmd, data); 1354 break; 1355 } 1356 1357 return (error); 1358} 1359 1360static void 1361stge_link_task(void *arg, int pending) 1362{ 1363 struct stge_softc *sc; 1364 struct mii_data *mii; 1365 uint32_t v, ac; 1366 int i; 1367 1368 sc = (struct stge_softc *)arg; 1369 STGE_LOCK(sc); 1370 1371 mii = device_get_softc(sc->sc_miibus); 1372 if (mii->mii_media_status & IFM_ACTIVE) { 1373 if (IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 1374 sc->sc_link = 1; 1375 } else 1376 sc->sc_link = 0; 1377 1378 sc->sc_MACCtrl = 0; 1379 if (((mii->mii_media_active & IFM_GMASK) & IFM_FDX) != 0) 1380 sc->sc_MACCtrl |= MC_DuplexSelect; 1381 if (((mii->mii_media_active & IFM_GMASK) & IFM_ETH_RXPAUSE) != 0) 1382 sc->sc_MACCtrl |= MC_RxFlowControlEnable; 1383 if (((mii->mii_media_active & IFM_GMASK) & IFM_ETH_TXPAUSE) != 0) 1384 sc->sc_MACCtrl |= MC_TxFlowControlEnable; 1385 /* 1386 * Update STGE_MACCtrl register depending on link status. 1387 * (duplex, flow control etc) 1388 */ 1389 v = ac = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; 1390 v &= ~(MC_DuplexSelect|MC_RxFlowControlEnable|MC_TxFlowControlEnable); 1391 v |= sc->sc_MACCtrl; 1392 CSR_WRITE_4(sc, STGE_MACCtrl, v); 1393 if (((ac ^ sc->sc_MACCtrl) & MC_DuplexSelect) != 0) { 1394 /* Duplex setting changed, reset Tx/Rx functions. */ 1395 ac = CSR_READ_4(sc, STGE_AsicCtrl); 1396 ac |= AC_TxReset | AC_RxReset; 1397 CSR_WRITE_4(sc, STGE_AsicCtrl, ac); 1398 for (i = 0; i < STGE_TIMEOUT; i++) { 1399 DELAY(100); 1400 if ((CSR_READ_4(sc, STGE_AsicCtrl) & AC_ResetBusy) == 0) 1401 break; 1402 } 1403 if (i == STGE_TIMEOUT) 1404 device_printf(sc->sc_dev, "reset failed to complete\n"); 1405 } 1406 STGE_UNLOCK(sc); 1407} 1408 1409static __inline int 1410stge_tx_error(struct stge_softc *sc) 1411{ 1412 uint32_t txstat; 1413 int error; 1414 1415 for (error = 0;;) { 1416 txstat = CSR_READ_4(sc, STGE_TxStatus); 1417 if ((txstat & TS_TxComplete) == 0) 1418 break; 1419 /* Tx underrun */ 1420 if ((txstat & TS_TxUnderrun) != 0) { 1421 /* 1422 * XXX 1423 * There should be a more better way to recover 1424 * from Tx underrun instead of a full reset. 1425 */ 1426 if (sc->sc_nerr++ < STGE_MAXERR) 1427 device_printf(sc->sc_dev, "Tx underrun, " 1428 "resetting...\n"); 1429 if (sc->sc_nerr == STGE_MAXERR) 1430 device_printf(sc->sc_dev, "too many errors; " 1431 "not reporting any more\n"); 1432 error = -1; 1433 break; 1434 } 1435 /* Maximum/Late collisions, Re-enable Tx MAC. */ 1436 if ((txstat & (TS_MaxCollisions|TS_LateCollision)) != 0) 1437 CSR_WRITE_4(sc, STGE_MACCtrl, 1438 (CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK) | 1439 MC_TxEnable); 1440 } 1441 1442 return (error); 1443} 1444 1445/* 1446 * stge_intr: 1447 * 1448 * Interrupt service routine. 1449 */ 1450static void 1451stge_intr(void *arg) 1452{ 1453 struct stge_softc *sc; 1454 struct ifnet *ifp; 1455 int reinit; 1456 uint16_t status; 1457 1458 sc = (struct stge_softc *)arg; 1459 ifp = sc->sc_ifp; 1460 1461 STGE_LOCK(sc); 1462 1463#ifdef DEVICE_POLLING 1464 if ((ifp->if_capenable & IFCAP_POLLING) != 0) 1465 goto done_locked; 1466#endif 1467 status = CSR_READ_2(sc, STGE_IntStatus); 1468 if (sc->sc_suspended || (status & IS_InterruptStatus) == 0) 1469 goto done_locked; 1470 1471 /* Disable interrupts. */ 1472 for (reinit = 0;;) { 1473 status = CSR_READ_2(sc, STGE_IntStatusAck); 1474 status &= sc->sc_IntEnable; 1475 if (status == 0) 1476 break; 1477 /* Host interface errors. */ 1478 if ((status & IS_HostError) != 0) { 1479 device_printf(sc->sc_dev, 1480 "Host interface error, resetting...\n"); 1481 reinit = 1; 1482 goto force_init; 1483 } 1484 1485 /* Receive interrupts. */ 1486 if ((status & IS_RxDMAComplete) != 0) { 1487 stge_rxeof(sc); 1488 if ((status & IS_RFDListEnd) != 0) 1489 CSR_WRITE_4(sc, STGE_DMACtrl, 1490 DMAC_RxDMAPollNow); 1491 } 1492 1493 /* Transmit interrupts. */ 1494 if ((status & (IS_TxDMAComplete | IS_TxComplete)) != 0) 1495 stge_txeof(sc); 1496 1497 /* Transmission errors.*/ 1498 if ((status & IS_TxComplete) != 0) { 1499 if ((reinit = stge_tx_error(sc)) != 0) 1500 break; 1501 } 1502 } 1503 1504force_init: 1505 if (reinit != 0) { 1506 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1507 stge_init_locked(sc); 1508 } 1509 1510 /* Re-enable interrupts. */ 1511 CSR_WRITE_2(sc, STGE_IntEnable, sc->sc_IntEnable); 1512 1513 /* Try to get more packets going. */ 1514 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1515 stge_start_locked(ifp); 1516 1517done_locked: 1518 STGE_UNLOCK(sc); 1519} 1520 1521/* 1522 * stge_txeof: 1523 * 1524 * Helper; handle transmit interrupts. 1525 */ 1526static void 1527stge_txeof(struct stge_softc *sc) 1528{ 1529 struct ifnet *ifp; 1530 struct stge_txdesc *txd; 1531 uint64_t control; 1532 int cons; 1533 1534 STGE_LOCK_ASSERT(sc); 1535 1536 ifp = sc->sc_ifp; 1537 1538 txd = STAILQ_FIRST(&sc->sc_cdata.stge_txbusyq); 1539 if (txd == NULL) 1540 return; 1541 bus_dmamap_sync(sc->sc_cdata.stge_tx_ring_tag, 1542 sc->sc_cdata.stge_tx_ring_map, BUS_DMASYNC_POSTREAD); 1543 1544 /* 1545 * Go through our Tx list and free mbufs for those 1546 * frames which have been transmitted. 1547 */ 1548 for (cons = sc->sc_cdata.stge_tx_cons;; 1549 cons = (cons + 1) % STGE_TX_RING_CNT) { 1550 if (sc->sc_cdata.stge_tx_cnt <= 0) 1551 break; 1552 control = le64toh(sc->sc_rdata.stge_tx_ring[cons].tfd_control); 1553 if ((control & TFD_TFDDone) == 0) 1554 break; 1555 sc->sc_cdata.stge_tx_cnt--; 1556 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1557 1558 bus_dmamap_sync(sc->sc_cdata.stge_tx_tag, txd->tx_dmamap, 1559 BUS_DMASYNC_POSTWRITE); 1560 bus_dmamap_unload(sc->sc_cdata.stge_tx_tag, txd->tx_dmamap); 1561 1562 /* Output counter is updated with statistics register */ 1563 m_freem(txd->tx_m); 1564 txd->tx_m = NULL; 1565 STAILQ_REMOVE_HEAD(&sc->sc_cdata.stge_txbusyq, tx_q); 1566 STAILQ_INSERT_TAIL(&sc->sc_cdata.stge_txfreeq, txd, tx_q); 1567 txd = STAILQ_FIRST(&sc->sc_cdata.stge_txbusyq); 1568 } 1569 sc->sc_cdata.stge_tx_cons = cons; 1570 if (sc->sc_cdata.stge_tx_cnt == 0) 1571 sc->sc_watchdog_timer = 0; 1572 1573 bus_dmamap_sync(sc->sc_cdata.stge_tx_ring_tag, 1574 sc->sc_cdata.stge_tx_ring_map, 1575 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1576} 1577 1578static __inline void 1579stge_discard_rxbuf(struct stge_softc *sc, int idx) 1580{ 1581 struct stge_rfd *rfd; 1582 1583 rfd = &sc->sc_rdata.stge_rx_ring[idx]; 1584 rfd->rfd_status = 0; 1585} 1586 1587#ifndef __NO_STRICT_ALIGNMENT 1588/* 1589 * It seems that TC9021's DMA engine has alignment restrictions in 1590 * DMA scatter operations. The first DMA segment has no address 1591 * alignment restrictins but the rest should be aligned on 4(?) bytes 1592 * boundary. Otherwise it would corrupt random memory. Since we don't 1593 * know which one is used for the first segment in advance we simply 1594 * don't align at all. 1595 * To avoid copying over an entire frame to align, we allocate a new 1596 * mbuf and copy ethernet header to the new mbuf. The new mbuf is 1597 * prepended into the existing mbuf chain. 1598 */ 1599static __inline struct mbuf * 1600stge_fixup_rx(struct stge_softc *sc, struct mbuf *m) 1601{ 1602 struct mbuf *n; 1603 1604 n = NULL; 1605 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) { 1606 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 1607 m->m_data += ETHER_HDR_LEN; 1608 n = m; 1609 } else { 1610 MGETHDR(n, M_NOWAIT, MT_DATA); 1611 if (n != NULL) { 1612 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 1613 m->m_data += ETHER_HDR_LEN; 1614 m->m_len -= ETHER_HDR_LEN; 1615 n->m_len = ETHER_HDR_LEN; 1616 M_MOVE_PKTHDR(n, m); 1617 n->m_next = m; 1618 } else 1619 m_freem(m); 1620 } 1621 1622 return (n); 1623} 1624#endif 1625 1626/* 1627 * stge_rxeof: 1628 * 1629 * Helper; handle receive interrupts. 1630 */ 1631static int 1632stge_rxeof(struct stge_softc *sc) 1633{ 1634 struct ifnet *ifp; 1635 struct stge_rxdesc *rxd; 1636 struct mbuf *mp, *m; 1637 uint64_t status64; 1638 uint32_t status; 1639 int cons, prog, rx_npkts; 1640 1641 STGE_LOCK_ASSERT(sc); 1642 1643 rx_npkts = 0; 1644 ifp = sc->sc_ifp; 1645 1646 bus_dmamap_sync(sc->sc_cdata.stge_rx_ring_tag, 1647 sc->sc_cdata.stge_rx_ring_map, BUS_DMASYNC_POSTREAD); 1648 1649 prog = 0; 1650 for (cons = sc->sc_cdata.stge_rx_cons; prog < STGE_RX_RING_CNT; 1651 prog++, cons = (cons + 1) % STGE_RX_RING_CNT) { 1652 status64 = le64toh(sc->sc_rdata.stge_rx_ring[cons].rfd_status); 1653 status = RFD_RxStatus(status64); 1654 if ((status & RFD_RFDDone) == 0) 1655 break; 1656#ifdef DEVICE_POLLING 1657 if (ifp->if_capenable & IFCAP_POLLING) { 1658 if (sc->sc_cdata.stge_rxcycles <= 0) 1659 break; 1660 sc->sc_cdata.stge_rxcycles--; 1661 } 1662#endif 1663 prog++; 1664 rxd = &sc->sc_cdata.stge_rxdesc[cons]; 1665 mp = rxd->rx_m; 1666 1667 /* 1668 * If the packet had an error, drop it. Note we count 1669 * the error later in the periodic stats update. 1670 */ 1671 if ((status & RFD_FrameEnd) != 0 && (status & 1672 (RFD_RxFIFOOverrun | RFD_RxRuntFrame | 1673 RFD_RxAlignmentError | RFD_RxFCSError | 1674 RFD_RxLengthError)) != 0) { 1675 stge_discard_rxbuf(sc, cons); 1676 if (sc->sc_cdata.stge_rxhead != NULL) { 1677 m_freem(sc->sc_cdata.stge_rxhead); 1678 STGE_RXCHAIN_RESET(sc); 1679 } 1680 continue; 1681 } 1682 /* 1683 * Add a new receive buffer to the ring. 1684 */ 1685 if (stge_newbuf(sc, cons) != 0) { 1686 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 1687 stge_discard_rxbuf(sc, cons); 1688 if (sc->sc_cdata.stge_rxhead != NULL) { 1689 m_freem(sc->sc_cdata.stge_rxhead); 1690 STGE_RXCHAIN_RESET(sc); 1691 } 1692 continue; 1693 } 1694 1695 if ((status & RFD_FrameEnd) != 0) 1696 mp->m_len = RFD_RxDMAFrameLen(status) - 1697 sc->sc_cdata.stge_rxlen; 1698 sc->sc_cdata.stge_rxlen += mp->m_len; 1699 1700 /* Chain mbufs. */ 1701 if (sc->sc_cdata.stge_rxhead == NULL) { 1702 sc->sc_cdata.stge_rxhead = mp; 1703 sc->sc_cdata.stge_rxtail = mp; 1704 } else { 1705 mp->m_flags &= ~M_PKTHDR; 1706 sc->sc_cdata.stge_rxtail->m_next = mp; 1707 sc->sc_cdata.stge_rxtail = mp; 1708 } 1709 1710 if ((status & RFD_FrameEnd) != 0) { 1711 m = sc->sc_cdata.stge_rxhead; 1712 m->m_pkthdr.rcvif = ifp; 1713 m->m_pkthdr.len = sc->sc_cdata.stge_rxlen; 1714 1715 if (m->m_pkthdr.len > sc->sc_if_framesize) { 1716 m_freem(m); 1717 STGE_RXCHAIN_RESET(sc); 1718 continue; 1719 } 1720 /* 1721 * Set the incoming checksum information for 1722 * the packet. 1723 */ 1724 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) { 1725 if ((status & RFD_IPDetected) != 0) { 1726 m->m_pkthdr.csum_flags |= 1727 CSUM_IP_CHECKED; 1728 if ((status & RFD_IPError) == 0) 1729 m->m_pkthdr.csum_flags |= 1730 CSUM_IP_VALID; 1731 } 1732 if (((status & RFD_TCPDetected) != 0 && 1733 (status & RFD_TCPError) == 0) || 1734 ((status & RFD_UDPDetected) != 0 && 1735 (status & RFD_UDPError) == 0)) { 1736 m->m_pkthdr.csum_flags |= 1737 (CSUM_DATA_VALID | CSUM_PSEUDO_HDR); 1738 m->m_pkthdr.csum_data = 0xffff; 1739 } 1740 } 1741 1742#ifndef __NO_STRICT_ALIGNMENT 1743 if (sc->sc_if_framesize > (MCLBYTES - ETHER_ALIGN)) { 1744 if ((m = stge_fixup_rx(sc, m)) == NULL) { 1745 STGE_RXCHAIN_RESET(sc); 1746 continue; 1747 } 1748 } 1749#endif 1750 /* Check for VLAN tagged packets. */ 1751 if ((status & RFD_VLANDetected) != 0 && 1752 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) { 1753 m->m_pkthdr.ether_vtag = RFD_TCI(status64); 1754 m->m_flags |= M_VLANTAG; 1755 } 1756 1757 STGE_UNLOCK(sc); 1758 /* Pass it on. */ 1759 (*ifp->if_input)(ifp, m); 1760 STGE_LOCK(sc); 1761 rx_npkts++; 1762 1763 STGE_RXCHAIN_RESET(sc); 1764 } 1765 } 1766 1767 if (prog > 0) { 1768 /* Update the consumer index. */ 1769 sc->sc_cdata.stge_rx_cons = cons; 1770 bus_dmamap_sync(sc->sc_cdata.stge_rx_ring_tag, 1771 sc->sc_cdata.stge_rx_ring_map, 1772 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1773 } 1774 return (rx_npkts); 1775} 1776 1777#ifdef DEVICE_POLLING 1778static int 1779stge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1780{ 1781 struct stge_softc *sc; 1782 uint16_t status; 1783 int rx_npkts; 1784 1785 rx_npkts = 0; 1786 sc = ifp->if_softc; 1787 STGE_LOCK(sc); 1788 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1789 STGE_UNLOCK(sc); 1790 return (rx_npkts); 1791 } 1792 1793 sc->sc_cdata.stge_rxcycles = count; 1794 rx_npkts = stge_rxeof(sc); 1795 stge_txeof(sc); 1796 1797 if (cmd == POLL_AND_CHECK_STATUS) { 1798 status = CSR_READ_2(sc, STGE_IntStatus); 1799 status &= sc->sc_IntEnable; 1800 if (status != 0) { 1801 if ((status & IS_HostError) != 0) { 1802 device_printf(sc->sc_dev, 1803 "Host interface error, resetting...\n"); 1804 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1805 stge_init_locked(sc); 1806 } 1807 if ((status & IS_TxComplete) != 0) { 1808 if (stge_tx_error(sc) != 0) { 1809 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1810 stge_init_locked(sc); 1811 } 1812 } 1813 } 1814 1815 } 1816 1817 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1818 stge_start_locked(ifp); 1819 1820 STGE_UNLOCK(sc); 1821 return (rx_npkts); 1822} 1823#endif /* DEVICE_POLLING */ 1824 1825/* 1826 * stge_tick: 1827 * 1828 * One second timer, used to tick the MII. 1829 */ 1830static void 1831stge_tick(void *arg) 1832{ 1833 struct stge_softc *sc; 1834 struct mii_data *mii; 1835 1836 sc = (struct stge_softc *)arg; 1837 1838 STGE_LOCK_ASSERT(sc); 1839 1840 mii = device_get_softc(sc->sc_miibus); 1841 mii_tick(mii); 1842 1843 /* Update statistics counters. */ 1844 stge_stats_update(sc); 1845 1846 /* 1847 * Relcaim any pending Tx descriptors to release mbufs in a 1848 * timely manner as we don't generate Tx completion interrupts 1849 * for every frame. This limits the delay to a maximum of one 1850 * second. 1851 */ 1852 if (sc->sc_cdata.stge_tx_cnt != 0) 1853 stge_txeof(sc); 1854 1855 stge_watchdog(sc); 1856 1857 callout_reset(&sc->sc_tick_ch, hz, stge_tick, sc); 1858} 1859 1860/* 1861 * stge_stats_update: 1862 * 1863 * Read the TC9021 statistics counters. 1864 */ 1865static void 1866stge_stats_update(struct stge_softc *sc) 1867{ 1868 struct ifnet *ifp; 1869 1870 STGE_LOCK_ASSERT(sc); 1871 1872 ifp = sc->sc_ifp; 1873 1874 CSR_READ_4(sc,STGE_OctetRcvOk); 1875 1876 if_inc_counter(ifp, IFCOUNTER_IPACKETS, CSR_READ_4(sc, STGE_FramesRcvdOk)); 1877 1878 if_inc_counter(ifp, IFCOUNTER_IERRORS, CSR_READ_2(sc, STGE_FramesLostRxErrors)); 1879 1880 CSR_READ_4(sc, STGE_OctetXmtdOk); 1881 1882 if_inc_counter(ifp, IFCOUNTER_OPACKETS, CSR_READ_4(sc, STGE_FramesXmtdOk)); 1883 1884 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1885 CSR_READ_4(sc, STGE_LateCollisions) + 1886 CSR_READ_4(sc, STGE_MultiColFrames) + 1887 CSR_READ_4(sc, STGE_SingleColFrames)); 1888 1889 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1890 CSR_READ_2(sc, STGE_FramesAbortXSColls) + 1891 CSR_READ_2(sc, STGE_FramesWEXDeferal)); 1892} 1893 1894/* 1895 * stge_reset: 1896 * 1897 * Perform a soft reset on the TC9021. 1898 */ 1899static void 1900stge_reset(struct stge_softc *sc, uint32_t how) 1901{ 1902 uint32_t ac; 1903 uint8_t v; 1904 int i, dv; 1905 1906 STGE_LOCK_ASSERT(sc); 1907 1908 dv = 5000; 1909 ac = CSR_READ_4(sc, STGE_AsicCtrl); 1910 switch (how) { 1911 case STGE_RESET_TX: 1912 ac |= AC_TxReset | AC_FIFO; 1913 dv = 100; 1914 break; 1915 case STGE_RESET_RX: 1916 ac |= AC_RxReset | AC_FIFO; 1917 dv = 100; 1918 break; 1919 case STGE_RESET_FULL: 1920 default: 1921 /* 1922 * Only assert RstOut if we're fiber. We need GMII clocks 1923 * to be present in order for the reset to complete on fiber 1924 * cards. 1925 */ 1926 ac |= AC_GlobalReset | AC_RxReset | AC_TxReset | 1927 AC_DMA | AC_FIFO | AC_Network | AC_Host | AC_AutoInit | 1928 (sc->sc_usefiber ? AC_RstOut : 0); 1929 break; 1930 } 1931 1932 CSR_WRITE_4(sc, STGE_AsicCtrl, ac); 1933 1934 /* Account for reset problem at 10Mbps. */ 1935 DELAY(dv); 1936 1937 for (i = 0; i < STGE_TIMEOUT; i++) { 1938 if ((CSR_READ_4(sc, STGE_AsicCtrl) & AC_ResetBusy) == 0) 1939 break; 1940 DELAY(dv); 1941 } 1942 1943 if (i == STGE_TIMEOUT) 1944 device_printf(sc->sc_dev, "reset failed to complete\n"); 1945 1946 /* Set LED, from Linux IPG driver. */ 1947 ac = CSR_READ_4(sc, STGE_AsicCtrl); 1948 ac &= ~(AC_LEDMode | AC_LEDSpeed | AC_LEDModeBit1); 1949 if ((sc->sc_led & 0x01) != 0) 1950 ac |= AC_LEDMode; 1951 if ((sc->sc_led & 0x03) != 0) 1952 ac |= AC_LEDModeBit1; 1953 if ((sc->sc_led & 0x08) != 0) 1954 ac |= AC_LEDSpeed; 1955 CSR_WRITE_4(sc, STGE_AsicCtrl, ac); 1956 1957 /* Set PHY, from Linux IPG driver */ 1958 v = CSR_READ_1(sc, STGE_PhySet); 1959 v &= ~(PS_MemLenb9b | PS_MemLen | PS_NonCompdet); 1960 v |= ((sc->sc_led & 0x70) >> 4); 1961 CSR_WRITE_1(sc, STGE_PhySet, v); 1962} 1963 1964/* 1965 * stge_init: [ ifnet interface function ] 1966 * 1967 * Initialize the interface. 1968 */ 1969static void 1970stge_init(void *xsc) 1971{ 1972 struct stge_softc *sc; 1973 1974 sc = (struct stge_softc *)xsc; 1975 STGE_LOCK(sc); 1976 stge_init_locked(sc); 1977 STGE_UNLOCK(sc); 1978} 1979 1980static void 1981stge_init_locked(struct stge_softc *sc) 1982{ 1983 struct ifnet *ifp; 1984 struct mii_data *mii; 1985 uint16_t eaddr[3]; 1986 uint32_t v; 1987 int error; 1988 1989 STGE_LOCK_ASSERT(sc); 1990 1991 ifp = sc->sc_ifp; 1992 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1993 return; 1994 mii = device_get_softc(sc->sc_miibus); 1995 1996 /* 1997 * Cancel any pending I/O. 1998 */ 1999 stge_stop(sc); 2000 2001 /* 2002 * Reset the chip to a known state. 2003 */ 2004 stge_reset(sc, STGE_RESET_FULL); 2005 2006 /* Init descriptors. */ 2007 error = stge_init_rx_ring(sc); 2008 if (error != 0) { 2009 device_printf(sc->sc_dev, 2010 "initialization failed: no memory for rx buffers\n"); 2011 stge_stop(sc); 2012 goto out; 2013 } 2014 stge_init_tx_ring(sc); 2015 2016 /* Set the station address. */ 2017 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); 2018 CSR_WRITE_2(sc, STGE_StationAddress0, htole16(eaddr[0])); 2019 CSR_WRITE_2(sc, STGE_StationAddress1, htole16(eaddr[1])); 2020 CSR_WRITE_2(sc, STGE_StationAddress2, htole16(eaddr[2])); 2021 2022 /* 2023 * Set the statistics masks. Disable all the RMON stats, 2024 * and disable selected stats in the non-RMON stats registers. 2025 */ 2026 CSR_WRITE_4(sc, STGE_RMONStatisticsMask, 0xffffffff); 2027 CSR_WRITE_4(sc, STGE_StatisticsMask, 2028 (1U << 1) | (1U << 2) | (1U << 3) | (1U << 4) | (1U << 5) | 2029 (1U << 6) | (1U << 7) | (1U << 8) | (1U << 9) | (1U << 10) | 2030 (1U << 13) | (1U << 14) | (1U << 15) | (1U << 19) | (1U << 20) | 2031 (1U << 21)); 2032 2033 /* Set up the receive filter. */ 2034 stge_set_filter(sc); 2035 /* Program multicast filter. */ 2036 stge_set_multi(sc); 2037 2038 /* 2039 * Give the transmit and receive ring to the chip. 2040 */ 2041 CSR_WRITE_4(sc, STGE_TFDListPtrHi, 2042 STGE_ADDR_HI(STGE_TX_RING_ADDR(sc, 0))); 2043 CSR_WRITE_4(sc, STGE_TFDListPtrLo, 2044 STGE_ADDR_LO(STGE_TX_RING_ADDR(sc, 0))); 2045 2046 CSR_WRITE_4(sc, STGE_RFDListPtrHi, 2047 STGE_ADDR_HI(STGE_RX_RING_ADDR(sc, 0))); 2048 CSR_WRITE_4(sc, STGE_RFDListPtrLo, 2049 STGE_ADDR_LO(STGE_RX_RING_ADDR(sc, 0))); 2050 2051 /* 2052 * Initialize the Tx auto-poll period. It's OK to make this number 2053 * large (255 is the max, but we use 127) -- we explicitly kick the 2054 * transmit engine when there's actually a packet. 2055 */ 2056 CSR_WRITE_1(sc, STGE_TxDMAPollPeriod, 127); 2057 2058 /* ..and the Rx auto-poll period. */ 2059 CSR_WRITE_1(sc, STGE_RxDMAPollPeriod, 1); 2060 2061 /* Initialize the Tx start threshold. */ 2062 CSR_WRITE_2(sc, STGE_TxStartThresh, sc->sc_txthresh); 2063 2064 /* Rx DMA thresholds, from Linux */ 2065 CSR_WRITE_1(sc, STGE_RxDMABurstThresh, 0x30); 2066 CSR_WRITE_1(sc, STGE_RxDMAUrgentThresh, 0x30); 2067 2068 /* Rx early threhold, from Linux */ 2069 CSR_WRITE_2(sc, STGE_RxEarlyThresh, 0x7ff); 2070 2071 /* Tx DMA thresholds, from Linux */ 2072 CSR_WRITE_1(sc, STGE_TxDMABurstThresh, 0x30); 2073 CSR_WRITE_1(sc, STGE_TxDMAUrgentThresh, 0x04); 2074 2075 /* 2076 * Initialize the Rx DMA interrupt control register. We 2077 * request an interrupt after every incoming packet, but 2078 * defer it for sc_rxint_dmawait us. When the number of 2079 * interrupts pending reaches STGE_RXINT_NFRAME, we stop 2080 * deferring the interrupt, and signal it immediately. 2081 */ 2082 CSR_WRITE_4(sc, STGE_RxDMAIntCtrl, 2083 RDIC_RxFrameCount(sc->sc_rxint_nframe) | 2084 RDIC_RxDMAWaitTime(STGE_RXINT_USECS2TICK(sc->sc_rxint_dmawait))); 2085 2086 /* 2087 * Initialize the interrupt mask. 2088 */ 2089 sc->sc_IntEnable = IS_HostError | IS_TxComplete | 2090 IS_TxDMAComplete | IS_RxDMAComplete | IS_RFDListEnd; 2091#ifdef DEVICE_POLLING 2092 /* Disable interrupts if we are polling. */ 2093 if ((ifp->if_capenable & IFCAP_POLLING) != 0) 2094 CSR_WRITE_2(sc, STGE_IntEnable, 0); 2095 else 2096#endif 2097 CSR_WRITE_2(sc, STGE_IntEnable, sc->sc_IntEnable); 2098 2099 /* 2100 * Configure the DMA engine. 2101 * XXX Should auto-tune TxBurstLimit. 2102 */ 2103 CSR_WRITE_4(sc, STGE_DMACtrl, sc->sc_DMACtrl | DMAC_TxBurstLimit(3)); 2104 2105 /* 2106 * Send a PAUSE frame when we reach 29,696 bytes in the Rx 2107 * FIFO, and send an un-PAUSE frame when we reach 3056 bytes 2108 * in the Rx FIFO. 2109 */ 2110 CSR_WRITE_2(sc, STGE_FlowOnTresh, 29696 / 16); 2111 CSR_WRITE_2(sc, STGE_FlowOffThresh, 3056 / 16); 2112 2113 /* 2114 * Set the maximum frame size. 2115 */ 2116 sc->sc_if_framesize = ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 2117 CSR_WRITE_2(sc, STGE_MaxFrameSize, sc->sc_if_framesize); 2118 2119 /* 2120 * Initialize MacCtrl -- do it before setting the media, 2121 * as setting the media will actually program the register. 2122 * 2123 * Note: We have to poke the IFS value before poking 2124 * anything else. 2125 */ 2126 /* Tx/Rx MAC should be disabled before programming IFS.*/ 2127 CSR_WRITE_4(sc, STGE_MACCtrl, MC_IFSSelect(MC_IFS96bit)); 2128 2129 stge_vlan_setup(sc); 2130 2131 if (sc->sc_rev >= 6) { /* >= B.2 */ 2132 /* Multi-frag frame bug work-around. */ 2133 CSR_WRITE_2(sc, STGE_DebugCtrl, 2134 CSR_READ_2(sc, STGE_DebugCtrl) | 0x0200); 2135 2136 /* Tx Poll Now bug work-around. */ 2137 CSR_WRITE_2(sc, STGE_DebugCtrl, 2138 CSR_READ_2(sc, STGE_DebugCtrl) | 0x0010); 2139 /* Tx Poll Now bug work-around. */ 2140 CSR_WRITE_2(sc, STGE_DebugCtrl, 2141 CSR_READ_2(sc, STGE_DebugCtrl) | 0x0020); 2142 } 2143 2144 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; 2145 v |= MC_StatisticsEnable | MC_TxEnable | MC_RxEnable; 2146 CSR_WRITE_4(sc, STGE_MACCtrl, v); 2147 /* 2148 * It seems that transmitting frames without checking the state of 2149 * Rx/Tx MAC wedge the hardware. 2150 */ 2151 stge_start_tx(sc); 2152 stge_start_rx(sc); 2153 2154 sc->sc_link = 0; 2155 /* 2156 * Set the current media. 2157 */ 2158 mii_mediachg(mii); 2159 2160 /* 2161 * Start the one second MII clock. 2162 */ 2163 callout_reset(&sc->sc_tick_ch, hz, stge_tick, sc); 2164 2165 /* 2166 * ...all done! 2167 */ 2168 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2169 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2170 2171 out: 2172 if (error != 0) 2173 device_printf(sc->sc_dev, "interface not running\n"); 2174} 2175 2176static void 2177stge_vlan_setup(struct stge_softc *sc) 2178{ 2179 struct ifnet *ifp; 2180 uint32_t v; 2181 2182 ifp = sc->sc_ifp; 2183 /* 2184 * The NIC always copy a VLAN tag regardless of STGE_MACCtrl 2185 * MC_AutoVLANuntagging bit. 2186 * MC_AutoVLANtagging bit selects which VLAN source to use 2187 * between STGE_VLANTag and TFC. However TFC TFD_VLANTagInsert 2188 * bit has priority over MC_AutoVLANtagging bit. So we always 2189 * use TFC instead of STGE_VLANTag register. 2190 */ 2191 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; 2192 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 2193 v |= MC_AutoVLANuntagging; 2194 else 2195 v &= ~MC_AutoVLANuntagging; 2196 CSR_WRITE_4(sc, STGE_MACCtrl, v); 2197} 2198 2199/* 2200 * Stop transmission on the interface. 2201 */ 2202static void 2203stge_stop(struct stge_softc *sc) 2204{ 2205 struct ifnet *ifp; 2206 struct stge_txdesc *txd; 2207 struct stge_rxdesc *rxd; 2208 uint32_t v; 2209 int i; 2210 2211 STGE_LOCK_ASSERT(sc); 2212 /* 2213 * Stop the one second clock. 2214 */ 2215 callout_stop(&sc->sc_tick_ch); 2216 sc->sc_watchdog_timer = 0; 2217 2218 /* 2219 * Disable interrupts. 2220 */ 2221 CSR_WRITE_2(sc, STGE_IntEnable, 0); 2222 2223 /* 2224 * Stop receiver, transmitter, and stats update. 2225 */ 2226 stge_stop_rx(sc); 2227 stge_stop_tx(sc); 2228 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; 2229 v |= MC_StatisticsDisable; 2230 CSR_WRITE_4(sc, STGE_MACCtrl, v); 2231 2232 /* 2233 * Stop the transmit and receive DMA. 2234 */ 2235 stge_dma_wait(sc); 2236 CSR_WRITE_4(sc, STGE_TFDListPtrHi, 0); 2237 CSR_WRITE_4(sc, STGE_TFDListPtrLo, 0); 2238 CSR_WRITE_4(sc, STGE_RFDListPtrHi, 0); 2239 CSR_WRITE_4(sc, STGE_RFDListPtrLo, 0); 2240 2241 /* 2242 * Free RX and TX mbufs still in the queues. 2243 */ 2244 for (i = 0; i < STGE_RX_RING_CNT; i++) { 2245 rxd = &sc->sc_cdata.stge_rxdesc[i]; 2246 if (rxd->rx_m != NULL) { 2247 bus_dmamap_sync(sc->sc_cdata.stge_rx_tag, 2248 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 2249 bus_dmamap_unload(sc->sc_cdata.stge_rx_tag, 2250 rxd->rx_dmamap); 2251 m_freem(rxd->rx_m); 2252 rxd->rx_m = NULL; 2253 } 2254 } 2255 for (i = 0; i < STGE_TX_RING_CNT; i++) { 2256 txd = &sc->sc_cdata.stge_txdesc[i]; 2257 if (txd->tx_m != NULL) { 2258 bus_dmamap_sync(sc->sc_cdata.stge_tx_tag, 2259 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2260 bus_dmamap_unload(sc->sc_cdata.stge_tx_tag, 2261 txd->tx_dmamap); 2262 m_freem(txd->tx_m); 2263 txd->tx_m = NULL; 2264 } 2265 } 2266 2267 /* 2268 * Mark the interface down and cancel the watchdog timer. 2269 */ 2270 ifp = sc->sc_ifp; 2271 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2272 sc->sc_link = 0; 2273} 2274 2275static void 2276stge_start_tx(struct stge_softc *sc) 2277{ 2278 uint32_t v; 2279 int i; 2280 2281 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; 2282 if ((v & MC_TxEnabled) != 0) 2283 return; 2284 v |= MC_TxEnable; 2285 CSR_WRITE_4(sc, STGE_MACCtrl, v); 2286 CSR_WRITE_1(sc, STGE_TxDMAPollPeriod, 127); 2287 for (i = STGE_TIMEOUT; i > 0; i--) { 2288 DELAY(10); 2289 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; 2290 if ((v & MC_TxEnabled) != 0) 2291 break; 2292 } 2293 if (i == 0) 2294 device_printf(sc->sc_dev, "Starting Tx MAC timed out\n"); 2295} 2296 2297static void 2298stge_start_rx(struct stge_softc *sc) 2299{ 2300 uint32_t v; 2301 int i; 2302 2303 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; 2304 if ((v & MC_RxEnabled) != 0) 2305 return; 2306 v |= MC_RxEnable; 2307 CSR_WRITE_4(sc, STGE_MACCtrl, v); 2308 CSR_WRITE_1(sc, STGE_RxDMAPollPeriod, 1); 2309 for (i = STGE_TIMEOUT; i > 0; i--) { 2310 DELAY(10); 2311 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; 2312 if ((v & MC_RxEnabled) != 0) 2313 break; 2314 } 2315 if (i == 0) 2316 device_printf(sc->sc_dev, "Starting Rx MAC timed out\n"); 2317} 2318 2319static void 2320stge_stop_tx(struct stge_softc *sc) 2321{ 2322 uint32_t v; 2323 int i; 2324 2325 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; 2326 if ((v & MC_TxEnabled) == 0) 2327 return; 2328 v |= MC_TxDisable; 2329 CSR_WRITE_4(sc, STGE_MACCtrl, v); 2330 for (i = STGE_TIMEOUT; i > 0; i--) { 2331 DELAY(10); 2332 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; 2333 if ((v & MC_TxEnabled) == 0) 2334 break; 2335 } 2336 if (i == 0) 2337 device_printf(sc->sc_dev, "Stopping Tx MAC timed out\n"); 2338} 2339 2340static void 2341stge_stop_rx(struct stge_softc *sc) 2342{ 2343 uint32_t v; 2344 int i; 2345 2346 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; 2347 if ((v & MC_RxEnabled) == 0) 2348 return; 2349 v |= MC_RxDisable; 2350 CSR_WRITE_4(sc, STGE_MACCtrl, v); 2351 for (i = STGE_TIMEOUT; i > 0; i--) { 2352 DELAY(10); 2353 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; 2354 if ((v & MC_RxEnabled) == 0) 2355 break; 2356 } 2357 if (i == 0) 2358 device_printf(sc->sc_dev, "Stopping Rx MAC timed out\n"); 2359} 2360 2361static void 2362stge_init_tx_ring(struct stge_softc *sc) 2363{ 2364 struct stge_ring_data *rd; 2365 struct stge_txdesc *txd; 2366 bus_addr_t addr; 2367 int i; 2368 2369 STAILQ_INIT(&sc->sc_cdata.stge_txfreeq); 2370 STAILQ_INIT(&sc->sc_cdata.stge_txbusyq); 2371 2372 sc->sc_cdata.stge_tx_prod = 0; 2373 sc->sc_cdata.stge_tx_cons = 0; 2374 sc->sc_cdata.stge_tx_cnt = 0; 2375 2376 rd = &sc->sc_rdata; 2377 bzero(rd->stge_tx_ring, STGE_TX_RING_SZ); 2378 for (i = 0; i < STGE_TX_RING_CNT; i++) { 2379 if (i == (STGE_TX_RING_CNT - 1)) 2380 addr = STGE_TX_RING_ADDR(sc, 0); 2381 else 2382 addr = STGE_TX_RING_ADDR(sc, i + 1); 2383 rd->stge_tx_ring[i].tfd_next = htole64(addr); 2384 rd->stge_tx_ring[i].tfd_control = htole64(TFD_TFDDone); 2385 txd = &sc->sc_cdata.stge_txdesc[i]; 2386 STAILQ_INSERT_TAIL(&sc->sc_cdata.stge_txfreeq, txd, tx_q); 2387 } 2388 2389 bus_dmamap_sync(sc->sc_cdata.stge_tx_ring_tag, 2390 sc->sc_cdata.stge_tx_ring_map, 2391 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2392 2393} 2394 2395static int 2396stge_init_rx_ring(struct stge_softc *sc) 2397{ 2398 struct stge_ring_data *rd; 2399 bus_addr_t addr; 2400 int i; 2401 2402 sc->sc_cdata.stge_rx_cons = 0; 2403 STGE_RXCHAIN_RESET(sc); 2404 2405 rd = &sc->sc_rdata; 2406 bzero(rd->stge_rx_ring, STGE_RX_RING_SZ); 2407 for (i = 0; i < STGE_RX_RING_CNT; i++) { 2408 if (stge_newbuf(sc, i) != 0) 2409 return (ENOBUFS); 2410 if (i == (STGE_RX_RING_CNT - 1)) 2411 addr = STGE_RX_RING_ADDR(sc, 0); 2412 else 2413 addr = STGE_RX_RING_ADDR(sc, i + 1); 2414 rd->stge_rx_ring[i].rfd_next = htole64(addr); 2415 rd->stge_rx_ring[i].rfd_status = 0; 2416 } 2417 2418 bus_dmamap_sync(sc->sc_cdata.stge_rx_ring_tag, 2419 sc->sc_cdata.stge_rx_ring_map, 2420 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2421 2422 return (0); 2423} 2424 2425/* 2426 * stge_newbuf: 2427 * 2428 * Add a receive buffer to the indicated descriptor. 2429 */ 2430static int 2431stge_newbuf(struct stge_softc *sc, int idx) 2432{ 2433 struct stge_rxdesc *rxd; 2434 struct stge_rfd *rfd; 2435 struct mbuf *m; 2436 bus_dma_segment_t segs[1]; 2437 bus_dmamap_t map; 2438 int nsegs; 2439 2440 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 2441 if (m == NULL) 2442 return (ENOBUFS); 2443 m->m_len = m->m_pkthdr.len = MCLBYTES; 2444 /* 2445 * The hardware requires 4bytes aligned DMA address when JUMBO 2446 * frame is used. 2447 */ 2448 if (sc->sc_if_framesize <= (MCLBYTES - ETHER_ALIGN)) 2449 m_adj(m, ETHER_ALIGN); 2450 2451 if (bus_dmamap_load_mbuf_sg(sc->sc_cdata.stge_rx_tag, 2452 sc->sc_cdata.stge_rx_sparemap, m, segs, &nsegs, 0) != 0) { 2453 m_freem(m); 2454 return (ENOBUFS); 2455 } 2456 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 2457 2458 rxd = &sc->sc_cdata.stge_rxdesc[idx]; 2459 if (rxd->rx_m != NULL) { 2460 bus_dmamap_sync(sc->sc_cdata.stge_rx_tag, rxd->rx_dmamap, 2461 BUS_DMASYNC_POSTREAD); 2462 bus_dmamap_unload(sc->sc_cdata.stge_rx_tag, rxd->rx_dmamap); 2463 } 2464 map = rxd->rx_dmamap; 2465 rxd->rx_dmamap = sc->sc_cdata.stge_rx_sparemap; 2466 sc->sc_cdata.stge_rx_sparemap = map; 2467 bus_dmamap_sync(sc->sc_cdata.stge_rx_tag, rxd->rx_dmamap, 2468 BUS_DMASYNC_PREREAD); 2469 rxd->rx_m = m; 2470 2471 rfd = &sc->sc_rdata.stge_rx_ring[idx]; 2472 rfd->rfd_frag.frag_word0 = 2473 htole64(FRAG_ADDR(segs[0].ds_addr) | FRAG_LEN(segs[0].ds_len)); 2474 rfd->rfd_status = 0; 2475 2476 return (0); 2477} 2478 2479/* 2480 * stge_set_filter: 2481 * 2482 * Set up the receive filter. 2483 */ 2484static void 2485stge_set_filter(struct stge_softc *sc) 2486{ 2487 struct ifnet *ifp; 2488 uint16_t mode; 2489 2490 STGE_LOCK_ASSERT(sc); 2491 2492 ifp = sc->sc_ifp; 2493 2494 mode = CSR_READ_2(sc, STGE_ReceiveMode); 2495 mode |= RM_ReceiveUnicast; 2496 if ((ifp->if_flags & IFF_BROADCAST) != 0) 2497 mode |= RM_ReceiveBroadcast; 2498 else 2499 mode &= ~RM_ReceiveBroadcast; 2500 if ((ifp->if_flags & IFF_PROMISC) != 0) 2501 mode |= RM_ReceiveAllFrames; 2502 else 2503 mode &= ~RM_ReceiveAllFrames; 2504 2505 CSR_WRITE_2(sc, STGE_ReceiveMode, mode); 2506} 2507 2508static void 2509stge_set_multi(struct stge_softc *sc) 2510{ 2511 struct ifnet *ifp; 2512 struct ifmultiaddr *ifma; 2513 uint32_t crc; 2514 uint32_t mchash[2]; 2515 uint16_t mode; 2516 int count; 2517 2518 STGE_LOCK_ASSERT(sc); 2519 2520 ifp = sc->sc_ifp; 2521 2522 mode = CSR_READ_2(sc, STGE_ReceiveMode); 2523 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 2524 if ((ifp->if_flags & IFF_PROMISC) != 0) 2525 mode |= RM_ReceiveAllFrames; 2526 else if ((ifp->if_flags & IFF_ALLMULTI) != 0) 2527 mode |= RM_ReceiveMulticast; 2528 CSR_WRITE_2(sc, STGE_ReceiveMode, mode); 2529 return; 2530 } 2531 2532 /* clear existing filters. */ 2533 CSR_WRITE_4(sc, STGE_HashTable0, 0); 2534 CSR_WRITE_4(sc, STGE_HashTable1, 0); 2535 2536 /* 2537 * Set up the multicast address filter by passing all multicast 2538 * addresses through a CRC generator, and then using the low-order 2539 * 6 bits as an index into the 64 bit multicast hash table. The 2540 * high order bits select the register, while the rest of the bits 2541 * select the bit within the register. 2542 */ 2543 2544 bzero(mchash, sizeof(mchash)); 2545 2546 count = 0; 2547 if_maddr_rlock(sc->sc_ifp); 2548 TAILQ_FOREACH(ifma, &sc->sc_ifp->if_multiaddrs, ifma_link) { 2549 if (ifma->ifma_addr->sa_family != AF_LINK) 2550 continue; 2551 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *) 2552 ifma->ifma_addr), ETHER_ADDR_LEN); 2553 2554 /* Just want the 6 least significant bits. */ 2555 crc &= 0x3f; 2556 2557 /* Set the corresponding bit in the hash table. */ 2558 mchash[crc >> 5] |= 1 << (crc & 0x1f); 2559 count++; 2560 } 2561 if_maddr_runlock(ifp); 2562 2563 mode &= ~(RM_ReceiveMulticast | RM_ReceiveAllFrames); 2564 if (count > 0) 2565 mode |= RM_ReceiveMulticastHash; 2566 else 2567 mode &= ~RM_ReceiveMulticastHash; 2568 2569 CSR_WRITE_4(sc, STGE_HashTable0, mchash[0]); 2570 CSR_WRITE_4(sc, STGE_HashTable1, mchash[1]); 2571 CSR_WRITE_2(sc, STGE_ReceiveMode, mode); 2572} 2573 2574static int 2575sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 2576{ 2577 int error, value; 2578 2579 if (!arg1) 2580 return (EINVAL); 2581 value = *(int *)arg1; 2582 error = sysctl_handle_int(oidp, &value, 0, req); 2583 if (error || !req->newptr) 2584 return (error); 2585 if (value < low || value > high) 2586 return (EINVAL); 2587 *(int *)arg1 = value; 2588 2589 return (0); 2590} 2591 2592static int 2593sysctl_hw_stge_rxint_nframe(SYSCTL_HANDLER_ARGS) 2594{ 2595 return (sysctl_int_range(oidp, arg1, arg2, req, 2596 STGE_RXINT_NFRAME_MIN, STGE_RXINT_NFRAME_MAX)); 2597} 2598 2599static int 2600sysctl_hw_stge_rxint_dmawait(SYSCTL_HANDLER_ARGS) 2601{ 2602 return (sysctl_int_range(oidp, arg1, arg2, req, 2603 STGE_RXINT_DMAWAIT_MIN, STGE_RXINT_DMAWAIT_MAX)); 2604} 2605