1160641Syongari/* $NetBSD: if_stge.c,v 1.32 2005/12/11 12:22:49 christos Exp $ */ 2160641Syongari 3160641Syongari/*- 4160641Syongari * Copyright (c) 2001 The NetBSD Foundation, Inc. 5160641Syongari * All rights reserved. 6160641Syongari * 7160641Syongari * This code is derived from software contributed to The NetBSD Foundation 8160641Syongari * by Jason R. Thorpe. 9160641Syongari * 10160641Syongari * Redistribution and use in source and binary forms, with or without 11160641Syongari * modification, are permitted provided that the following conditions 12160641Syongari * are met: 13160641Syongari * 1. Redistributions of source code must retain the above copyright 14160641Syongari * notice, this list of conditions and the following disclaimer. 15160641Syongari * 2. Redistributions in binary form must reproduce the above copyright 16160641Syongari * notice, this list of conditions and the following disclaimer in the 17160641Syongari * documentation and/or other materials provided with the distribution. 18160641Syongari * 19160641Syongari * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20160641Syongari * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21160641Syongari * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22160641Syongari * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23160641Syongari * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24160641Syongari * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25160641Syongari * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26160641Syongari * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27160641Syongari * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28160641Syongari * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29160641Syongari * POSSIBILITY OF SUCH DAMAGE. 30160641Syongari */ 31160641Syongari 32160641Syongari/* 33160641Syongari * Device driver for the Sundance Tech. TC9021 10/100/1000 34160641Syongari * Ethernet controller. 35160641Syongari */ 36160641Syongari 37160641Syongari#include <sys/cdefs.h> 38160641Syongari__FBSDID("$FreeBSD$"); 39160641Syongari 40160641Syongari#ifdef HAVE_KERNEL_OPTION_HEADERS 41160641Syongari#include "opt_device_polling.h" 42160641Syongari#endif 43160641Syongari 44160641Syongari#include <sys/param.h> 45160641Syongari#include <sys/systm.h> 46160641Syongari#include <sys/endian.h> 47160641Syongari#include <sys/mbuf.h> 48160641Syongari#include <sys/malloc.h> 49160641Syongari#include <sys/kernel.h> 50160641Syongari#include <sys/module.h> 51160641Syongari#include <sys/socket.h> 52160641Syongari#include <sys/sockio.h> 53160641Syongari#include <sys/sysctl.h> 54160641Syongari#include <sys/taskqueue.h> 55160641Syongari 56160641Syongari#include <net/bpf.h> 57160641Syongari#include <net/ethernet.h> 58160641Syongari#include <net/if.h> 59257176Sglebius#include <net/if_var.h> 60160641Syongari#include <net/if_dl.h> 61160641Syongari#include <net/if_media.h> 62160641Syongari#include <net/if_types.h> 63160641Syongari#include <net/if_vlan_var.h> 64160641Syongari 65160641Syongari#include <machine/bus.h> 66160641Syongari#include <machine/resource.h> 67160641Syongari#include <sys/bus.h> 68160641Syongari#include <sys/rman.h> 69160641Syongari 70160641Syongari#include <dev/mii/mii.h> 71226995Smarius#include <dev/mii/mii_bitbang.h> 72160641Syongari#include <dev/mii/miivar.h> 73160641Syongari 74160641Syongari#include <dev/pci/pcireg.h> 75160641Syongari#include <dev/pci/pcivar.h> 76160641Syongari 77160641Syongari#include <dev/stge/if_stgereg.h> 78160641Syongari 79160641Syongari#define STGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 80160641Syongari 81160641SyongariMODULE_DEPEND(stge, pci, 1, 1, 1); 82160641SyongariMODULE_DEPEND(stge, ether, 1, 1, 1); 83160641SyongariMODULE_DEPEND(stge, miibus, 1, 1, 1); 84160641Syongari 85160641Syongari/* "device miibus" required. See GENERIC if you get errors here. */ 86160641Syongari#include "miibus_if.h" 87160641Syongari 88160641Syongari/* 89160641Syongari * Devices supported by this driver. 90160641Syongari */ 91226995Smariusstatic const struct stge_product { 92160641Syongari uint16_t stge_vendorid; 93160641Syongari uint16_t stge_deviceid; 94160641Syongari const char *stge_name; 95242625Sdim} stge_products[] = { 96160641Syongari { VENDOR_SUNDANCETI, DEVICEID_SUNDANCETI_ST1023, 97160641Syongari "Sundance ST-1023 Gigabit Ethernet" }, 98160641Syongari 99160641Syongari { VENDOR_SUNDANCETI, DEVICEID_SUNDANCETI_ST2021, 100160641Syongari "Sundance ST-2021 Gigabit Ethernet" }, 101160641Syongari 102160641Syongari { VENDOR_TAMARACK, DEVICEID_TAMARACK_TC9021, 103160641Syongari "Tamarack TC9021 Gigabit Ethernet" }, 104160641Syongari 105160641Syongari { VENDOR_TAMARACK, DEVICEID_TAMARACK_TC9021_ALT, 106160641Syongari "Tamarack TC9021 Gigabit Ethernet" }, 107160641Syongari 108160641Syongari /* 109160641Syongari * The Sundance sample boards use the Sundance vendor ID, 110160641Syongari * but the Tamarack product ID. 111160641Syongari */ 112160641Syongari { VENDOR_SUNDANCETI, DEVICEID_TAMARACK_TC9021, 113160641Syongari "Sundance TC9021 Gigabit Ethernet" }, 114160641Syongari 115160641Syongari { VENDOR_SUNDANCETI, DEVICEID_TAMARACK_TC9021_ALT, 116160641Syongari "Sundance TC9021 Gigabit Ethernet" }, 117160641Syongari 118160641Syongari { VENDOR_DLINK, DEVICEID_DLINK_DL4000, 119160641Syongari "D-Link DL-4000 Gigabit Ethernet" }, 120160641Syongari 121160641Syongari { VENDOR_ANTARES, DEVICEID_ANTARES_TC9021, 122160641Syongari "Antares Gigabit Ethernet" } 123160641Syongari}; 124160641Syongari 125160641Syongaristatic int stge_probe(device_t); 126160641Syongaristatic int stge_attach(device_t); 127160641Syongaristatic int stge_detach(device_t); 128173839Syongaristatic int stge_shutdown(device_t); 129160641Syongaristatic int stge_suspend(device_t); 130160641Syongaristatic int stge_resume(device_t); 131160641Syongari 132160641Syongaristatic int stge_encap(struct stge_softc *, struct mbuf **); 133160641Syongaristatic void stge_start(struct ifnet *); 134160641Syongaristatic void stge_start_locked(struct ifnet *); 135169157Syongaristatic void stge_watchdog(struct stge_softc *); 136160641Syongaristatic int stge_ioctl(struct ifnet *, u_long, caddr_t); 137160641Syongaristatic void stge_init(void *); 138160641Syongaristatic void stge_init_locked(struct stge_softc *); 139160641Syongaristatic void stge_vlan_setup(struct stge_softc *); 140160641Syongaristatic void stge_stop(struct stge_softc *); 141160641Syongaristatic void stge_start_tx(struct stge_softc *); 142160641Syongaristatic void stge_start_rx(struct stge_softc *); 143160641Syongaristatic void stge_stop_tx(struct stge_softc *); 144160641Syongaristatic void stge_stop_rx(struct stge_softc *); 145160641Syongari 146160641Syongaristatic void stge_reset(struct stge_softc *, uint32_t); 147160641Syongaristatic int stge_eeprom_wait(struct stge_softc *); 148160641Syongaristatic void stge_read_eeprom(struct stge_softc *, int, uint16_t *); 149160641Syongaristatic void stge_tick(void *); 150160641Syongaristatic void stge_stats_update(struct stge_softc *); 151160641Syongaristatic void stge_set_filter(struct stge_softc *); 152160641Syongaristatic void stge_set_multi(struct stge_softc *); 153160641Syongari 154160641Syongaristatic void stge_link_task(void *, int); 155160641Syongaristatic void stge_intr(void *); 156160641Syongaristatic __inline int stge_tx_error(struct stge_softc *); 157160641Syongaristatic void stge_txeof(struct stge_softc *); 158193096Sattiliostatic int stge_rxeof(struct stge_softc *); 159160641Syongaristatic __inline void stge_discard_rxbuf(struct stge_softc *, int); 160160641Syongaristatic int stge_newbuf(struct stge_softc *, int); 161160641Syongari#ifndef __NO_STRICT_ALIGNMENT 162160641Syongaristatic __inline struct mbuf *stge_fixup_rx(struct stge_softc *, struct mbuf *); 163160641Syongari#endif 164160641Syongari 165160641Syongaristatic int stge_miibus_readreg(device_t, int, int); 166160641Syongaristatic int stge_miibus_writereg(device_t, int, int, int); 167160641Syongaristatic void stge_miibus_statchg(device_t); 168160641Syongaristatic int stge_mediachange(struct ifnet *); 169160641Syongaristatic void stge_mediastatus(struct ifnet *, struct ifmediareq *); 170160641Syongari 171160641Syongaristatic void stge_dmamap_cb(void *, bus_dma_segment_t *, int, int); 172160641Syongaristatic int stge_dma_alloc(struct stge_softc *); 173160641Syongaristatic void stge_dma_free(struct stge_softc *); 174160641Syongaristatic void stge_dma_wait(struct stge_softc *); 175160641Syongaristatic void stge_init_tx_ring(struct stge_softc *); 176160641Syongaristatic int stge_init_rx_ring(struct stge_softc *); 177160641Syongari#ifdef DEVICE_POLLING 178193096Sattiliostatic int stge_poll(struct ifnet *, enum poll_cmd, int); 179160641Syongari#endif 180160641Syongari 181175315Syongaristatic void stge_setwol(struct stge_softc *); 182160641Syongaristatic int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 183160641Syongaristatic int sysctl_hw_stge_rxint_nframe(SYSCTL_HANDLER_ARGS); 184160641Syongaristatic int sysctl_hw_stge_rxint_dmawait(SYSCTL_HANDLER_ARGS); 185160641Syongari 186226995Smarius/* 187226995Smarius * MII bit-bang glue 188226995Smarius */ 189226995Smariusstatic uint32_t stge_mii_bitbang_read(device_t); 190226995Smariusstatic void stge_mii_bitbang_write(device_t, uint32_t); 191226995Smarius 192226995Smariusstatic const struct mii_bitbang_ops stge_mii_bitbang_ops = { 193226995Smarius stge_mii_bitbang_read, 194226995Smarius stge_mii_bitbang_write, 195226995Smarius { 196226995Smarius PC_MgmtData, /* MII_BIT_MDO */ 197226995Smarius PC_MgmtData, /* MII_BIT_MDI */ 198226995Smarius PC_MgmtClk, /* MII_BIT_MDC */ 199226995Smarius PC_MgmtDir, /* MII_BIT_DIR_HOST_PHY */ 200226995Smarius 0, /* MII_BIT_DIR_PHY_HOST */ 201226995Smarius } 202226995Smarius}; 203226995Smarius 204160641Syongaristatic device_method_t stge_methods[] = { 205160641Syongari /* Device interface */ 206160641Syongari DEVMETHOD(device_probe, stge_probe), 207160641Syongari DEVMETHOD(device_attach, stge_attach), 208160641Syongari DEVMETHOD(device_detach, stge_detach), 209160641Syongari DEVMETHOD(device_shutdown, stge_shutdown), 210160641Syongari DEVMETHOD(device_suspend, stge_suspend), 211160641Syongari DEVMETHOD(device_resume, stge_resume), 212160641Syongari 213160641Syongari /* MII interface */ 214160641Syongari DEVMETHOD(miibus_readreg, stge_miibus_readreg), 215160641Syongari DEVMETHOD(miibus_writereg, stge_miibus_writereg), 216160641Syongari DEVMETHOD(miibus_statchg, stge_miibus_statchg), 217160641Syongari 218227848Smarius DEVMETHOD_END 219160641Syongari}; 220160641Syongari 221160641Syongaristatic driver_t stge_driver = { 222160641Syongari "stge", 223160641Syongari stge_methods, 224160641Syongari sizeof(struct stge_softc) 225160641Syongari}; 226160641Syongari 227160641Syongaristatic devclass_t stge_devclass; 228160641Syongari 229160641SyongariDRIVER_MODULE(stge, pci, stge_driver, stge_devclass, 0, 0); 230160641SyongariDRIVER_MODULE(miibus, stge, miibus_driver, miibus_devclass, 0, 0); 231160641Syongari 232160641Syongaristatic struct resource_spec stge_res_spec_io[] = { 233160641Syongari { SYS_RES_IOPORT, PCIR_BAR(0), RF_ACTIVE }, 234160641Syongari { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 235160641Syongari { -1, 0, 0 } 236160641Syongari}; 237160641Syongari 238160641Syongaristatic struct resource_spec stge_res_spec_mem[] = { 239160641Syongari { SYS_RES_MEMORY, PCIR_BAR(1), RF_ACTIVE }, 240160641Syongari { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 241160641Syongari { -1, 0, 0 } 242160641Syongari}; 243160641Syongari 244160641Syongari/* 245226995Smarius * stge_mii_bitbang_read: [mii bit-bang interface function] 246226995Smarius * 247226995Smarius * Read the MII serial port for the MII bit-bang module. 248160641Syongari */ 249226995Smariusstatic uint32_t 250226995Smariusstge_mii_bitbang_read(device_t dev) 251160641Syongari{ 252226995Smarius struct stge_softc *sc; 253226995Smarius uint32_t val; 254160641Syongari 255226995Smarius sc = device_get_softc(dev); 256160641Syongari 257226995Smarius val = CSR_READ_1(sc, STGE_PhyCtrl); 258226995Smarius CSR_BARRIER(sc, STGE_PhyCtrl, 1, 259226995Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 260226995Smarius return (val); 261160641Syongari} 262160641Syongari 263160641Syongari/* 264226995Smarius * stge_mii_bitbang_write: [mii big-bang interface function] 265226995Smarius * 266226995Smarius * Write the MII serial port for the MII bit-bang module. 267160641Syongari */ 268160641Syongaristatic void 269226995Smariusstge_mii_bitbang_write(device_t dev, uint32_t val) 270160641Syongari{ 271226995Smarius struct stge_softc *sc; 272160641Syongari 273226995Smarius sc = device_get_softc(dev); 274160641Syongari 275226995Smarius CSR_WRITE_1(sc, STGE_PhyCtrl, val); 276226995Smarius CSR_BARRIER(sc, STGE_PhyCtrl, 1, 277226995Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 278160641Syongari} 279160641Syongari 280160641Syongari/* 281160641Syongari * sc_miibus_readreg: [mii interface function] 282160641Syongari * 283160641Syongari * Read a PHY register on the MII of the TC9021. 284160641Syongari */ 285160641Syongaristatic int 286160641Syongaristge_miibus_readreg(device_t dev, int phy, int reg) 287160641Syongari{ 288160641Syongari struct stge_softc *sc; 289226995Smarius int error, val; 290160641Syongari 291160641Syongari sc = device_get_softc(dev); 292160641Syongari 293160641Syongari if (reg == STGE_PhyCtrl) { 294160641Syongari /* XXX allow ip1000phy read STGE_PhyCtrl register. */ 295160641Syongari STGE_MII_LOCK(sc); 296160641Syongari error = CSR_READ_1(sc, STGE_PhyCtrl); 297160641Syongari STGE_MII_UNLOCK(sc); 298160641Syongari return (error); 299160641Syongari } 300160641Syongari 301160641Syongari STGE_MII_LOCK(sc); 302226995Smarius val = mii_bitbang_readreg(dev, &stge_mii_bitbang_ops, phy, reg); 303160641Syongari STGE_MII_UNLOCK(sc); 304226995Smarius return (val); 305160641Syongari} 306160641Syongari 307160641Syongari/* 308160641Syongari * stge_miibus_writereg: [mii interface function] 309160641Syongari * 310160641Syongari * Write a PHY register on the MII of the TC9021. 311160641Syongari */ 312160641Syongaristatic int 313160641Syongaristge_miibus_writereg(device_t dev, int phy, int reg, int val) 314160641Syongari{ 315160641Syongari struct stge_softc *sc; 316160641Syongari 317160641Syongari sc = device_get_softc(dev); 318160641Syongari 319160641Syongari STGE_MII_LOCK(sc); 320226995Smarius mii_bitbang_writereg(dev, &stge_mii_bitbang_ops, phy, reg, val); 321160641Syongari STGE_MII_UNLOCK(sc); 322160641Syongari return (0); 323160641Syongari} 324160641Syongari 325160641Syongari/* 326160641Syongari * stge_miibus_statchg: [mii interface function] 327160641Syongari * 328160641Syongari * Callback from MII layer when media changes. 329160641Syongari */ 330160641Syongaristatic void 331160641Syongaristge_miibus_statchg(device_t dev) 332160641Syongari{ 333160641Syongari struct stge_softc *sc; 334160641Syongari 335160641Syongari sc = device_get_softc(dev); 336160641Syongari taskqueue_enqueue(taskqueue_swi, &sc->sc_link_task); 337160641Syongari} 338160641Syongari 339160641Syongari/* 340160641Syongari * stge_mediastatus: [ifmedia interface function] 341160641Syongari * 342160641Syongari * Get the current interface media status. 343160641Syongari */ 344160641Syongaristatic void 345160641Syongaristge_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 346160641Syongari{ 347160641Syongari struct stge_softc *sc; 348160641Syongari struct mii_data *mii; 349160641Syongari 350160641Syongari sc = ifp->if_softc; 351160641Syongari mii = device_get_softc(sc->sc_miibus); 352160641Syongari 353160641Syongari mii_pollstat(mii); 354160641Syongari ifmr->ifm_status = mii->mii_media_status; 355160641Syongari ifmr->ifm_active = mii->mii_media_active; 356160641Syongari} 357160641Syongari 358160641Syongari/* 359160641Syongari * stge_mediachange: [ifmedia interface function] 360160641Syongari * 361160641Syongari * Set hardware to newly-selected media. 362160641Syongari */ 363160641Syongaristatic int 364160641Syongaristge_mediachange(struct ifnet *ifp) 365160641Syongari{ 366160641Syongari struct stge_softc *sc; 367160641Syongari struct mii_data *mii; 368160641Syongari 369160641Syongari sc = ifp->if_softc; 370160641Syongari mii = device_get_softc(sc->sc_miibus); 371160641Syongari mii_mediachg(mii); 372160641Syongari 373160641Syongari return (0); 374160641Syongari} 375160641Syongari 376160641Syongaristatic int 377160641Syongaristge_eeprom_wait(struct stge_softc *sc) 378160641Syongari{ 379160641Syongari int i; 380160641Syongari 381160641Syongari for (i = 0; i < STGE_TIMEOUT; i++) { 382160641Syongari DELAY(1000); 383160641Syongari if ((CSR_READ_2(sc, STGE_EepromCtrl) & EC_EepromBusy) == 0) 384160641Syongari return (0); 385160641Syongari } 386160641Syongari return (1); 387160641Syongari} 388160641Syongari 389160641Syongari/* 390160641Syongari * stge_read_eeprom: 391160641Syongari * 392160641Syongari * Read data from the serial EEPROM. 393160641Syongari */ 394160641Syongaristatic void 395160641Syongaristge_read_eeprom(struct stge_softc *sc, int offset, uint16_t *data) 396160641Syongari{ 397160641Syongari 398160641Syongari if (stge_eeprom_wait(sc)) 399160641Syongari device_printf(sc->sc_dev, "EEPROM failed to come ready\n"); 400160641Syongari 401160641Syongari CSR_WRITE_2(sc, STGE_EepromCtrl, 402160641Syongari EC_EepromAddress(offset) | EC_EepromOpcode(EC_OP_RR)); 403160641Syongari if (stge_eeprom_wait(sc)) 404160641Syongari device_printf(sc->sc_dev, "EEPROM read timed out\n"); 405160641Syongari *data = CSR_READ_2(sc, STGE_EepromData); 406160641Syongari} 407160641Syongari 408160641Syongari 409160641Syongaristatic int 410160641Syongaristge_probe(device_t dev) 411160641Syongari{ 412226995Smarius const struct stge_product *sp; 413160641Syongari int i; 414160641Syongari uint16_t vendor, devid; 415160641Syongari 416160641Syongari vendor = pci_get_vendor(dev); 417160641Syongari devid = pci_get_device(dev); 418160641Syongari sp = stge_products; 419298307Spfg for (i = 0; i < nitems(stge_products); i++, sp++) { 420160641Syongari if (vendor == sp->stge_vendorid && 421160641Syongari devid == sp->stge_deviceid) { 422160641Syongari device_set_desc(dev, sp->stge_name); 423160641Syongari return (BUS_PROBE_DEFAULT); 424160641Syongari } 425160641Syongari } 426160641Syongari 427160641Syongari return (ENXIO); 428160641Syongari} 429160641Syongari 430160641Syongaristatic int 431160641Syongaristge_attach(device_t dev) 432160641Syongari{ 433160641Syongari struct stge_softc *sc; 434160641Syongari struct ifnet *ifp; 435160641Syongari uint8_t enaddr[ETHER_ADDR_LEN]; 436213893Smarius int error, flags, i; 437160641Syongari uint16_t cmd; 438160641Syongari uint32_t val; 439160641Syongari 440160641Syongari error = 0; 441160641Syongari sc = device_get_softc(dev); 442160641Syongari sc->sc_dev = dev; 443160641Syongari 444160641Syongari mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 445160641Syongari MTX_DEF); 446160641Syongari mtx_init(&sc->sc_mii_mtx, "stge_mii_mutex", NULL, MTX_DEF); 447160641Syongari callout_init_mtx(&sc->sc_tick_ch, &sc->sc_mtx, 0); 448160641Syongari TASK_INIT(&sc->sc_link_task, 0, stge_link_task, sc); 449160641Syongari 450160641Syongari /* 451160641Syongari * Map the device. 452160641Syongari */ 453160641Syongari pci_enable_busmaster(dev); 454160641Syongari cmd = pci_read_config(dev, PCIR_COMMAND, 2); 455160641Syongari val = pci_read_config(dev, PCIR_BAR(1), 4); 456254263Sscottl if (PCI_BAR_IO(val)) 457160641Syongari sc->sc_spec = stge_res_spec_mem; 458160641Syongari else { 459160641Syongari val = pci_read_config(dev, PCIR_BAR(0), 4); 460254263Sscottl if (!PCI_BAR_IO(val)) { 461160641Syongari device_printf(sc->sc_dev, "couldn't locate IO BAR\n"); 462160641Syongari error = ENXIO; 463160641Syongari goto fail; 464160641Syongari } 465160641Syongari sc->sc_spec = stge_res_spec_io; 466160641Syongari } 467160641Syongari error = bus_alloc_resources(dev, sc->sc_spec, sc->sc_res); 468160641Syongari if (error != 0) { 469160641Syongari device_printf(dev, "couldn't allocate %s resources\n", 470160641Syongari sc->sc_spec == stge_res_spec_mem ? "memory" : "I/O"); 471160641Syongari goto fail; 472160641Syongari } 473160641Syongari sc->sc_rev = pci_get_revid(dev); 474160641Syongari 475160641Syongari SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 476160641Syongari SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 477160641Syongari "rxint_nframe", CTLTYPE_INT|CTLFLAG_RW, &sc->sc_rxint_nframe, 0, 478160641Syongari sysctl_hw_stge_rxint_nframe, "I", "stge rx interrupt nframe"); 479160641Syongari 480160641Syongari SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 481160641Syongari SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 482160641Syongari "rxint_dmawait", CTLTYPE_INT|CTLFLAG_RW, &sc->sc_rxint_dmawait, 0, 483160641Syongari sysctl_hw_stge_rxint_dmawait, "I", "stge rx interrupt dmawait"); 484160641Syongari 485160641Syongari /* Pull in device tunables. */ 486160641Syongari sc->sc_rxint_nframe = STGE_RXINT_NFRAME_DEFAULT; 487160641Syongari error = resource_int_value(device_get_name(dev), device_get_unit(dev), 488160641Syongari "rxint_nframe", &sc->sc_rxint_nframe); 489160641Syongari if (error == 0) { 490160641Syongari if (sc->sc_rxint_nframe < STGE_RXINT_NFRAME_MIN || 491160641Syongari sc->sc_rxint_nframe > STGE_RXINT_NFRAME_MAX) { 492160641Syongari device_printf(dev, "rxint_nframe value out of range; " 493160641Syongari "using default: %d\n", STGE_RXINT_NFRAME_DEFAULT); 494160641Syongari sc->sc_rxint_nframe = STGE_RXINT_NFRAME_DEFAULT; 495160641Syongari } 496160641Syongari } 497160641Syongari 498160641Syongari sc->sc_rxint_dmawait = STGE_RXINT_DMAWAIT_DEFAULT; 499160641Syongari error = resource_int_value(device_get_name(dev), device_get_unit(dev), 500160641Syongari "rxint_dmawait", &sc->sc_rxint_dmawait); 501160641Syongari if (error == 0) { 502160641Syongari if (sc->sc_rxint_dmawait < STGE_RXINT_DMAWAIT_MIN || 503160641Syongari sc->sc_rxint_dmawait > STGE_RXINT_DMAWAIT_MAX) { 504160641Syongari device_printf(dev, "rxint_dmawait value out of range; " 505160641Syongari "using default: %d\n", STGE_RXINT_DMAWAIT_DEFAULT); 506160641Syongari sc->sc_rxint_dmawait = STGE_RXINT_DMAWAIT_DEFAULT; 507160641Syongari } 508160641Syongari } 509160641Syongari 510295735Syongari if ((error = stge_dma_alloc(sc)) != 0) 511160641Syongari goto fail; 512160641Syongari 513160641Syongari /* 514160641Syongari * Determine if we're copper or fiber. It affects how we 515160641Syongari * reset the card. 516160641Syongari */ 517160641Syongari if (CSR_READ_4(sc, STGE_AsicCtrl) & AC_PhyMedia) 518160641Syongari sc->sc_usefiber = 1; 519160641Syongari else 520160641Syongari sc->sc_usefiber = 0; 521160641Syongari 522160641Syongari /* Load LED configuration from EEPROM. */ 523160641Syongari stge_read_eeprom(sc, STGE_EEPROM_LEDMode, &sc->sc_led); 524160641Syongari 525160641Syongari /* 526160641Syongari * Reset the chip to a known state. 527160641Syongari */ 528160641Syongari STGE_LOCK(sc); 529160641Syongari stge_reset(sc, STGE_RESET_FULL); 530160641Syongari STGE_UNLOCK(sc); 531160641Syongari 532160641Syongari /* 533160641Syongari * Reading the station address from the EEPROM doesn't seem 534160641Syongari * to work, at least on my sample boards. Instead, since 535160641Syongari * the reset sequence does AutoInit, read it from the station 536160641Syongari * address registers. For Sundance 1023 you can only read it 537160641Syongari * from EEPROM. 538160641Syongari */ 539160641Syongari if (pci_get_device(dev) != DEVICEID_SUNDANCETI_ST1023) { 540160641Syongari uint16_t v; 541160641Syongari 542160641Syongari v = CSR_READ_2(sc, STGE_StationAddress0); 543160641Syongari enaddr[0] = v & 0xff; 544160641Syongari enaddr[1] = v >> 8; 545160641Syongari v = CSR_READ_2(sc, STGE_StationAddress1); 546160641Syongari enaddr[2] = v & 0xff; 547160641Syongari enaddr[3] = v >> 8; 548160641Syongari v = CSR_READ_2(sc, STGE_StationAddress2); 549160641Syongari enaddr[4] = v & 0xff; 550160641Syongari enaddr[5] = v >> 8; 551160641Syongari sc->sc_stge1023 = 0; 552160641Syongari } else { 553160641Syongari uint16_t myaddr[ETHER_ADDR_LEN / 2]; 554160641Syongari for (i = 0; i <ETHER_ADDR_LEN / 2; i++) { 555160641Syongari stge_read_eeprom(sc, STGE_EEPROM_StationAddress0 + i, 556160641Syongari &myaddr[i]); 557160641Syongari myaddr[i] = le16toh(myaddr[i]); 558160641Syongari } 559160641Syongari bcopy(myaddr, enaddr, sizeof(enaddr)); 560160641Syongari sc->sc_stge1023 = 1; 561160641Syongari } 562160641Syongari 563160641Syongari ifp = sc->sc_ifp = if_alloc(IFT_ETHER); 564160641Syongari if (ifp == NULL) { 565160641Syongari device_printf(sc->sc_dev, "failed to if_alloc()\n"); 566160641Syongari error = ENXIO; 567160641Syongari goto fail; 568160641Syongari } 569160641Syongari 570160641Syongari ifp->if_softc = sc; 571160641Syongari if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 572160641Syongari ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 573160641Syongari ifp->if_ioctl = stge_ioctl; 574160641Syongari ifp->if_start = stge_start; 575160641Syongari ifp->if_init = stge_init; 576160641Syongari ifp->if_snd.ifq_drv_maxlen = STGE_TX_RING_CNT - 1; 577160641Syongari IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 578160641Syongari IFQ_SET_READY(&ifp->if_snd); 579160641Syongari /* Revision B3 and earlier chips have checksum bug. */ 580160641Syongari if (sc->sc_rev >= 0x0c) { 581160641Syongari ifp->if_hwassist = STGE_CSUM_FEATURES; 582160641Syongari ifp->if_capabilities = IFCAP_HWCSUM; 583160641Syongari } else { 584160641Syongari ifp->if_hwassist = 0; 585160641Syongari ifp->if_capabilities = 0; 586160641Syongari } 587175315Syongari ifp->if_capabilities |= IFCAP_WOL_MAGIC; 588160641Syongari ifp->if_capenable = ifp->if_capabilities; 589160641Syongari 590160641Syongari /* 591160641Syongari * Read some important bits from the PhyCtrl register. 592160641Syongari */ 593160641Syongari sc->sc_PhyCtrl = CSR_READ_1(sc, STGE_PhyCtrl) & 594160641Syongari (PC_PhyDuplexPolarity | PC_PhyLnkPolarity); 595160641Syongari 596160641Syongari /* Set up MII bus. */ 597215297Smarius flags = MIIF_DOPAUSE; 598213893Smarius if (sc->sc_rev >= 0x40 && sc->sc_rev <= 0x4e) 599213893Smarius flags |= MIIF_MACPRIV0; 600213893Smarius error = mii_attach(sc->sc_dev, &sc->sc_miibus, ifp, stge_mediachange, 601213893Smarius stge_mediastatus, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 602213893Smarius flags); 603213893Smarius if (error != 0) { 604213893Smarius device_printf(sc->sc_dev, "attaching PHYs failed\n"); 605160641Syongari goto fail; 606160641Syongari } 607160641Syongari 608160641Syongari ether_ifattach(ifp, enaddr); 609160641Syongari 610160641Syongari /* VLAN capability setup */ 611160641Syongari ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; 612160641Syongari if (sc->sc_rev >= 0x0c) 613160641Syongari ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 614160641Syongari ifp->if_capenable = ifp->if_capabilities; 615160641Syongari#ifdef DEVICE_POLLING 616160641Syongari ifp->if_capabilities |= IFCAP_POLLING; 617160641Syongari#endif 618160641Syongari /* 619160641Syongari * Tell the upper layer(s) we support long frames. 620160641Syongari * Must appear after the call to ether_ifattach() because 621160641Syongari * ether_ifattach() sets ifi_hdrlen to the default value. 622160641Syongari */ 623270856Sglebius ifp->if_hdrlen = sizeof(struct ether_vlan_header); 624160641Syongari 625160641Syongari /* 626160641Syongari * The manual recommends disabling early transmit, so we 627160641Syongari * do. It's disabled anyway, if using IP checksumming, 628160641Syongari * since the entire packet must be in the FIFO in order 629160641Syongari * for the chip to perform the checksum. 630160641Syongari */ 631160641Syongari sc->sc_txthresh = 0x0fff; 632160641Syongari 633160641Syongari /* 634160641Syongari * Disable MWI if the PCI layer tells us to. 635160641Syongari */ 636160641Syongari sc->sc_DMACtrl = 0; 637160641Syongari if ((cmd & PCIM_CMD_MWRICEN) == 0) 638160641Syongari sc->sc_DMACtrl |= DMAC_MWIDisable; 639160641Syongari 640160641Syongari /* 641160641Syongari * Hookup IRQ 642160641Syongari */ 643160641Syongari error = bus_setup_intr(dev, sc->sc_res[1], INTR_TYPE_NET | INTR_MPSAFE, 644166901Spiso NULL, stge_intr, sc, &sc->sc_ih); 645160641Syongari if (error != 0) { 646160641Syongari ether_ifdetach(ifp); 647160641Syongari device_printf(sc->sc_dev, "couldn't set up IRQ\n"); 648160641Syongari sc->sc_ifp = NULL; 649160641Syongari goto fail; 650160641Syongari } 651160641Syongari 652160641Syongarifail: 653160641Syongari if (error != 0) 654160641Syongari stge_detach(dev); 655160641Syongari 656160641Syongari return (error); 657160641Syongari} 658160641Syongari 659160641Syongaristatic int 660160641Syongaristge_detach(device_t dev) 661160641Syongari{ 662160641Syongari struct stge_softc *sc; 663160641Syongari struct ifnet *ifp; 664160641Syongari 665160641Syongari sc = device_get_softc(dev); 666160641Syongari 667160641Syongari ifp = sc->sc_ifp; 668160641Syongari#ifdef DEVICE_POLLING 669160641Syongari if (ifp && ifp->if_capenable & IFCAP_POLLING) 670160641Syongari ether_poll_deregister(ifp); 671160641Syongari#endif 672160641Syongari if (device_is_attached(dev)) { 673160641Syongari STGE_LOCK(sc); 674160641Syongari /* XXX */ 675160641Syongari sc->sc_detach = 1; 676160641Syongari stge_stop(sc); 677160641Syongari STGE_UNLOCK(sc); 678160641Syongari callout_drain(&sc->sc_tick_ch); 679160641Syongari taskqueue_drain(taskqueue_swi, &sc->sc_link_task); 680160641Syongari ether_ifdetach(ifp); 681160641Syongari } 682160641Syongari 683160641Syongari if (sc->sc_miibus != NULL) { 684160641Syongari device_delete_child(dev, sc->sc_miibus); 685160641Syongari sc->sc_miibus = NULL; 686160641Syongari } 687160641Syongari bus_generic_detach(dev); 688160641Syongari stge_dma_free(sc); 689160641Syongari 690160641Syongari if (ifp != NULL) { 691160641Syongari if_free(ifp); 692160641Syongari sc->sc_ifp = NULL; 693160641Syongari } 694160641Syongari 695160641Syongari if (sc->sc_ih) { 696160641Syongari bus_teardown_intr(dev, sc->sc_res[1], sc->sc_ih); 697160641Syongari sc->sc_ih = NULL; 698160641Syongari } 699160641Syongari bus_release_resources(dev, sc->sc_spec, sc->sc_res); 700160641Syongari 701160641Syongari mtx_destroy(&sc->sc_mii_mtx); 702160641Syongari mtx_destroy(&sc->sc_mtx); 703160641Syongari 704160641Syongari return (0); 705160641Syongari} 706160641Syongari 707160641Syongaristruct stge_dmamap_arg { 708160641Syongari bus_addr_t stge_busaddr; 709160641Syongari}; 710160641Syongari 711160641Syongaristatic void 712160641Syongaristge_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 713160641Syongari{ 714160641Syongari struct stge_dmamap_arg *ctx; 715160641Syongari 716160641Syongari if (error != 0) 717160641Syongari return; 718160641Syongari 719160641Syongari ctx = (struct stge_dmamap_arg *)arg; 720160641Syongari ctx->stge_busaddr = segs[0].ds_addr; 721160641Syongari} 722160641Syongari 723160641Syongaristatic int 724160641Syongaristge_dma_alloc(struct stge_softc *sc) 725160641Syongari{ 726160641Syongari struct stge_dmamap_arg ctx; 727160641Syongari struct stge_txdesc *txd; 728160641Syongari struct stge_rxdesc *rxd; 729160641Syongari int error, i; 730160641Syongari 731160641Syongari /* create parent tag. */ 732166165Smarius error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev),/* parent */ 733160641Syongari 1, 0, /* algnmnt, boundary */ 734160641Syongari STGE_DMA_MAXADDR, /* lowaddr */ 735160641Syongari BUS_SPACE_MAXADDR, /* highaddr */ 736160641Syongari NULL, NULL, /* filter, filterarg */ 737160641Syongari BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 738160641Syongari 0, /* nsegments */ 739160641Syongari BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 740160641Syongari 0, /* flags */ 741160641Syongari NULL, NULL, /* lockfunc, lockarg */ 742160641Syongari &sc->sc_cdata.stge_parent_tag); 743160641Syongari if (error != 0) { 744160641Syongari device_printf(sc->sc_dev, "failed to create parent DMA tag\n"); 745160641Syongari goto fail; 746160641Syongari } 747160641Syongari /* create tag for Tx ring. */ 748160641Syongari error = bus_dma_tag_create(sc->sc_cdata.stge_parent_tag,/* parent */ 749160641Syongari STGE_RING_ALIGN, 0, /* algnmnt, boundary */ 750160641Syongari BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 751160641Syongari BUS_SPACE_MAXADDR, /* highaddr */ 752160641Syongari NULL, NULL, /* filter, filterarg */ 753160641Syongari STGE_TX_RING_SZ, /* maxsize */ 754160641Syongari 1, /* nsegments */ 755160641Syongari STGE_TX_RING_SZ, /* maxsegsize */ 756160641Syongari 0, /* flags */ 757160641Syongari NULL, NULL, /* lockfunc, lockarg */ 758160641Syongari &sc->sc_cdata.stge_tx_ring_tag); 759160641Syongari if (error != 0) { 760160641Syongari device_printf(sc->sc_dev, 761160641Syongari "failed to allocate Tx ring DMA tag\n"); 762160641Syongari goto fail; 763160641Syongari } 764160641Syongari 765160641Syongari /* create tag for Rx ring. */ 766160641Syongari error = bus_dma_tag_create(sc->sc_cdata.stge_parent_tag,/* parent */ 767160641Syongari STGE_RING_ALIGN, 0, /* algnmnt, boundary */ 768160641Syongari BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 769160641Syongari BUS_SPACE_MAXADDR, /* highaddr */ 770160641Syongari NULL, NULL, /* filter, filterarg */ 771160641Syongari STGE_RX_RING_SZ, /* maxsize */ 772160641Syongari 1, /* nsegments */ 773160641Syongari STGE_RX_RING_SZ, /* maxsegsize */ 774160641Syongari 0, /* flags */ 775160641Syongari NULL, NULL, /* lockfunc, lockarg */ 776160641Syongari &sc->sc_cdata.stge_rx_ring_tag); 777160641Syongari if (error != 0) { 778160641Syongari device_printf(sc->sc_dev, 779160641Syongari "failed to allocate Rx ring DMA tag\n"); 780160641Syongari goto fail; 781160641Syongari } 782160641Syongari 783160641Syongari /* create tag for Tx buffers. */ 784160641Syongari error = bus_dma_tag_create(sc->sc_cdata.stge_parent_tag,/* parent */ 785160641Syongari 1, 0, /* algnmnt, boundary */ 786160641Syongari BUS_SPACE_MAXADDR, /* lowaddr */ 787160641Syongari BUS_SPACE_MAXADDR, /* highaddr */ 788160641Syongari NULL, NULL, /* filter, filterarg */ 789160641Syongari MCLBYTES * STGE_MAXTXSEGS, /* maxsize */ 790160641Syongari STGE_MAXTXSEGS, /* nsegments */ 791160641Syongari MCLBYTES, /* maxsegsize */ 792160641Syongari 0, /* flags */ 793160641Syongari NULL, NULL, /* lockfunc, lockarg */ 794160641Syongari &sc->sc_cdata.stge_tx_tag); 795160641Syongari if (error != 0) { 796160641Syongari device_printf(sc->sc_dev, "failed to allocate Tx DMA tag\n"); 797160641Syongari goto fail; 798160641Syongari } 799160641Syongari 800160641Syongari /* create tag for Rx buffers. */ 801160641Syongari error = bus_dma_tag_create(sc->sc_cdata.stge_parent_tag,/* parent */ 802160641Syongari 1, 0, /* algnmnt, boundary */ 803160641Syongari BUS_SPACE_MAXADDR, /* lowaddr */ 804160641Syongari BUS_SPACE_MAXADDR, /* highaddr */ 805160641Syongari NULL, NULL, /* filter, filterarg */ 806160641Syongari MCLBYTES, /* maxsize */ 807160641Syongari 1, /* nsegments */ 808160641Syongari MCLBYTES, /* maxsegsize */ 809160641Syongari 0, /* flags */ 810160641Syongari NULL, NULL, /* lockfunc, lockarg */ 811160641Syongari &sc->sc_cdata.stge_rx_tag); 812160641Syongari if (error != 0) { 813160641Syongari device_printf(sc->sc_dev, "failed to allocate Rx DMA tag\n"); 814160641Syongari goto fail; 815160641Syongari } 816160641Syongari 817160641Syongari /* allocate DMA'able memory and load the DMA map for Tx ring. */ 818160641Syongari error = bus_dmamem_alloc(sc->sc_cdata.stge_tx_ring_tag, 819219545Smarius (void **)&sc->sc_rdata.stge_tx_ring, BUS_DMA_NOWAIT | 820219545Smarius BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->sc_cdata.stge_tx_ring_map); 821160641Syongari if (error != 0) { 822160641Syongari device_printf(sc->sc_dev, 823160641Syongari "failed to allocate DMA'able memory for Tx ring\n"); 824160641Syongari goto fail; 825160641Syongari } 826160641Syongari 827160641Syongari ctx.stge_busaddr = 0; 828160641Syongari error = bus_dmamap_load(sc->sc_cdata.stge_tx_ring_tag, 829160641Syongari sc->sc_cdata.stge_tx_ring_map, sc->sc_rdata.stge_tx_ring, 830160641Syongari STGE_TX_RING_SZ, stge_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 831160641Syongari if (error != 0 || ctx.stge_busaddr == 0) { 832160641Syongari device_printf(sc->sc_dev, 833160641Syongari "failed to load DMA'able memory for Tx ring\n"); 834160641Syongari goto fail; 835160641Syongari } 836160641Syongari sc->sc_rdata.stge_tx_ring_paddr = ctx.stge_busaddr; 837160641Syongari 838160641Syongari /* allocate DMA'able memory and load the DMA map for Rx ring. */ 839160641Syongari error = bus_dmamem_alloc(sc->sc_cdata.stge_rx_ring_tag, 840219545Smarius (void **)&sc->sc_rdata.stge_rx_ring, BUS_DMA_NOWAIT | 841219545Smarius BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->sc_cdata.stge_rx_ring_map); 842160641Syongari if (error != 0) { 843160641Syongari device_printf(sc->sc_dev, 844160641Syongari "failed to allocate DMA'able memory for Rx ring\n"); 845160641Syongari goto fail; 846160641Syongari } 847160641Syongari 848160641Syongari ctx.stge_busaddr = 0; 849160641Syongari error = bus_dmamap_load(sc->sc_cdata.stge_rx_ring_tag, 850160641Syongari sc->sc_cdata.stge_rx_ring_map, sc->sc_rdata.stge_rx_ring, 851160641Syongari STGE_RX_RING_SZ, stge_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 852160641Syongari if (error != 0 || ctx.stge_busaddr == 0) { 853160641Syongari device_printf(sc->sc_dev, 854160641Syongari "failed to load DMA'able memory for Rx ring\n"); 855160641Syongari goto fail; 856160641Syongari } 857160641Syongari sc->sc_rdata.stge_rx_ring_paddr = ctx.stge_busaddr; 858160641Syongari 859160641Syongari /* create DMA maps for Tx buffers. */ 860160641Syongari for (i = 0; i < STGE_TX_RING_CNT; i++) { 861160641Syongari txd = &sc->sc_cdata.stge_txdesc[i]; 862160641Syongari txd->tx_m = NULL; 863160641Syongari txd->tx_dmamap = 0; 864160641Syongari error = bus_dmamap_create(sc->sc_cdata.stge_tx_tag, 0, 865160641Syongari &txd->tx_dmamap); 866160641Syongari if (error != 0) { 867160641Syongari device_printf(sc->sc_dev, 868160641Syongari "failed to create Tx dmamap\n"); 869160641Syongari goto fail; 870160641Syongari } 871160641Syongari } 872160641Syongari /* create DMA maps for Rx buffers. */ 873160641Syongari if ((error = bus_dmamap_create(sc->sc_cdata.stge_rx_tag, 0, 874160641Syongari &sc->sc_cdata.stge_rx_sparemap)) != 0) { 875160641Syongari device_printf(sc->sc_dev, "failed to create spare Rx dmamap\n"); 876160641Syongari goto fail; 877160641Syongari } 878160641Syongari for (i = 0; i < STGE_RX_RING_CNT; i++) { 879160641Syongari rxd = &sc->sc_cdata.stge_rxdesc[i]; 880160641Syongari rxd->rx_m = NULL; 881160641Syongari rxd->rx_dmamap = 0; 882160641Syongari error = bus_dmamap_create(sc->sc_cdata.stge_rx_tag, 0, 883160641Syongari &rxd->rx_dmamap); 884160641Syongari if (error != 0) { 885160641Syongari device_printf(sc->sc_dev, 886160641Syongari "failed to create Rx dmamap\n"); 887160641Syongari goto fail; 888160641Syongari } 889160641Syongari } 890160641Syongari 891160641Syongarifail: 892160641Syongari return (error); 893160641Syongari} 894160641Syongari 895160641Syongaristatic void 896160641Syongaristge_dma_free(struct stge_softc *sc) 897160641Syongari{ 898160641Syongari struct stge_txdesc *txd; 899160641Syongari struct stge_rxdesc *rxd; 900160641Syongari int i; 901160641Syongari 902160641Syongari /* Tx ring */ 903160641Syongari if (sc->sc_cdata.stge_tx_ring_tag) { 904267363Sjhb if (sc->sc_rdata.stge_tx_ring_paddr) 905160641Syongari bus_dmamap_unload(sc->sc_cdata.stge_tx_ring_tag, 906160641Syongari sc->sc_cdata.stge_tx_ring_map); 907267363Sjhb if (sc->sc_rdata.stge_tx_ring) 908160641Syongari bus_dmamem_free(sc->sc_cdata.stge_tx_ring_tag, 909160641Syongari sc->sc_rdata.stge_tx_ring, 910160641Syongari sc->sc_cdata.stge_tx_ring_map); 911160641Syongari sc->sc_rdata.stge_tx_ring = NULL; 912267363Sjhb sc->sc_rdata.stge_tx_ring_paddr = 0; 913160641Syongari bus_dma_tag_destroy(sc->sc_cdata.stge_tx_ring_tag); 914160641Syongari sc->sc_cdata.stge_tx_ring_tag = NULL; 915160641Syongari } 916160641Syongari /* Rx ring */ 917160641Syongari if (sc->sc_cdata.stge_rx_ring_tag) { 918267363Sjhb if (sc->sc_rdata.stge_rx_ring_paddr) 919160641Syongari bus_dmamap_unload(sc->sc_cdata.stge_rx_ring_tag, 920160641Syongari sc->sc_cdata.stge_rx_ring_map); 921267363Sjhb if (sc->sc_rdata.stge_rx_ring) 922160641Syongari bus_dmamem_free(sc->sc_cdata.stge_rx_ring_tag, 923160641Syongari sc->sc_rdata.stge_rx_ring, 924160641Syongari sc->sc_cdata.stge_rx_ring_map); 925160641Syongari sc->sc_rdata.stge_rx_ring = NULL; 926267363Sjhb sc->sc_rdata.stge_rx_ring_paddr = 0; 927160641Syongari bus_dma_tag_destroy(sc->sc_cdata.stge_rx_ring_tag); 928160641Syongari sc->sc_cdata.stge_rx_ring_tag = NULL; 929160641Syongari } 930160641Syongari /* Tx buffers */ 931160641Syongari if (sc->sc_cdata.stge_tx_tag) { 932160641Syongari for (i = 0; i < STGE_TX_RING_CNT; i++) { 933160641Syongari txd = &sc->sc_cdata.stge_txdesc[i]; 934160641Syongari if (txd->tx_dmamap) { 935160641Syongari bus_dmamap_destroy(sc->sc_cdata.stge_tx_tag, 936160641Syongari txd->tx_dmamap); 937160641Syongari txd->tx_dmamap = 0; 938160641Syongari } 939160641Syongari } 940160641Syongari bus_dma_tag_destroy(sc->sc_cdata.stge_tx_tag); 941160641Syongari sc->sc_cdata.stge_tx_tag = NULL; 942160641Syongari } 943160641Syongari /* Rx buffers */ 944160641Syongari if (sc->sc_cdata.stge_rx_tag) { 945160641Syongari for (i = 0; i < STGE_RX_RING_CNT; i++) { 946160641Syongari rxd = &sc->sc_cdata.stge_rxdesc[i]; 947160641Syongari if (rxd->rx_dmamap) { 948160641Syongari bus_dmamap_destroy(sc->sc_cdata.stge_rx_tag, 949160641Syongari rxd->rx_dmamap); 950160641Syongari rxd->rx_dmamap = 0; 951160641Syongari } 952160641Syongari } 953160641Syongari if (sc->sc_cdata.stge_rx_sparemap) { 954160641Syongari bus_dmamap_destroy(sc->sc_cdata.stge_rx_tag, 955160641Syongari sc->sc_cdata.stge_rx_sparemap); 956160641Syongari sc->sc_cdata.stge_rx_sparemap = 0; 957160641Syongari } 958160641Syongari bus_dma_tag_destroy(sc->sc_cdata.stge_rx_tag); 959160641Syongari sc->sc_cdata.stge_rx_tag = NULL; 960160641Syongari } 961160641Syongari 962160641Syongari if (sc->sc_cdata.stge_parent_tag) { 963160641Syongari bus_dma_tag_destroy(sc->sc_cdata.stge_parent_tag); 964160641Syongari sc->sc_cdata.stge_parent_tag = NULL; 965160641Syongari } 966160641Syongari} 967160641Syongari 968160641Syongari/* 969160641Syongari * stge_shutdown: 970160641Syongari * 971160641Syongari * Make sure the interface is stopped at reboot time. 972160641Syongari */ 973173839Syongaristatic int 974160641Syongaristge_shutdown(device_t dev) 975160641Syongari{ 976160641Syongari 977175315Syongari return (stge_suspend(dev)); 978175315Syongari} 979160641Syongari 980175315Syongaristatic void 981175315Syongaristge_setwol(struct stge_softc *sc) 982175315Syongari{ 983175315Syongari struct ifnet *ifp; 984175315Syongari uint8_t v; 985173839Syongari 986175315Syongari STGE_LOCK_ASSERT(sc); 987175315Syongari 988175315Syongari ifp = sc->sc_ifp; 989175315Syongari v = CSR_READ_1(sc, STGE_WakeEvent); 990175315Syongari /* Disable all WOL bits. */ 991175315Syongari v &= ~(WE_WakePktEnable | WE_MagicPktEnable | WE_LinkEventEnable | 992175315Syongari WE_WakeOnLanEnable); 993175315Syongari if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 994175315Syongari v |= WE_MagicPktEnable | WE_WakeOnLanEnable; 995175315Syongari CSR_WRITE_1(sc, STGE_WakeEvent, v); 996175315Syongari /* Reset Tx and prevent transmission. */ 997175315Syongari CSR_WRITE_4(sc, STGE_AsicCtrl, 998175315Syongari CSR_READ_4(sc, STGE_AsicCtrl) | AC_TxReset); 999175315Syongari /* 1000175315Syongari * TC9021 automatically reset link speed to 100Mbps when it's put 1001175315Syongari * into sleep so there is no need to try to resetting link speed. 1002175315Syongari */ 1003160641Syongari} 1004160641Syongari 1005160641Syongaristatic int 1006160641Syongaristge_suspend(device_t dev) 1007160641Syongari{ 1008160641Syongari struct stge_softc *sc; 1009160641Syongari 1010160641Syongari sc = device_get_softc(dev); 1011160641Syongari 1012160641Syongari STGE_LOCK(sc); 1013160641Syongari stge_stop(sc); 1014160641Syongari sc->sc_suspended = 1; 1015175315Syongari stge_setwol(sc); 1016160641Syongari STGE_UNLOCK(sc); 1017160641Syongari 1018160641Syongari return (0); 1019160641Syongari} 1020160641Syongari 1021160641Syongaristatic int 1022160641Syongaristge_resume(device_t dev) 1023160641Syongari{ 1024160641Syongari struct stge_softc *sc; 1025160641Syongari struct ifnet *ifp; 1026175315Syongari uint8_t v; 1027160641Syongari 1028160641Syongari sc = device_get_softc(dev); 1029160641Syongari 1030160641Syongari STGE_LOCK(sc); 1031175315Syongari /* 1032175315Syongari * Clear WOL bits, so special frames wouldn't interfere 1033175315Syongari * normal Rx operation anymore. 1034175315Syongari */ 1035175315Syongari v = CSR_READ_1(sc, STGE_WakeEvent); 1036175315Syongari v &= ~(WE_WakePktEnable | WE_MagicPktEnable | WE_LinkEventEnable | 1037175315Syongari WE_WakeOnLanEnable); 1038175315Syongari CSR_WRITE_1(sc, STGE_WakeEvent, v); 1039160641Syongari ifp = sc->sc_ifp; 1040160641Syongari if (ifp->if_flags & IFF_UP) 1041160641Syongari stge_init_locked(sc); 1042160641Syongari 1043160641Syongari sc->sc_suspended = 0; 1044160641Syongari STGE_UNLOCK(sc); 1045160641Syongari 1046160641Syongari return (0); 1047160641Syongari} 1048160641Syongari 1049160641Syongaristatic void 1050160641Syongaristge_dma_wait(struct stge_softc *sc) 1051160641Syongari{ 1052160641Syongari int i; 1053160641Syongari 1054160641Syongari for (i = 0; i < STGE_TIMEOUT; i++) { 1055160641Syongari DELAY(2); 1056160641Syongari if ((CSR_READ_4(sc, STGE_DMACtrl) & DMAC_TxDMAInProg) == 0) 1057160641Syongari break; 1058160641Syongari } 1059160641Syongari 1060160641Syongari if (i == STGE_TIMEOUT) 1061160641Syongari device_printf(sc->sc_dev, "DMA wait timed out\n"); 1062160641Syongari} 1063160641Syongari 1064160641Syongaristatic int 1065160641Syongaristge_encap(struct stge_softc *sc, struct mbuf **m_head) 1066160641Syongari{ 1067160641Syongari struct stge_txdesc *txd; 1068160641Syongari struct stge_tfd *tfd; 1069161235Syongari struct mbuf *m; 1070160641Syongari bus_dma_segment_t txsegs[STGE_MAXTXSEGS]; 1071160641Syongari int error, i, nsegs, si; 1072160641Syongari uint64_t csum_flags, tfc; 1073160641Syongari 1074160641Syongari STGE_LOCK_ASSERT(sc); 1075160641Syongari 1076160641Syongari if ((txd = STAILQ_FIRST(&sc->sc_cdata.stge_txfreeq)) == NULL) 1077160641Syongari return (ENOBUFS); 1078160641Syongari 1079160641Syongari error = bus_dmamap_load_mbuf_sg(sc->sc_cdata.stge_tx_tag, 1080161235Syongari txd->tx_dmamap, *m_head, txsegs, &nsegs, 0); 1081160641Syongari if (error == EFBIG) { 1082243857Sglebius m = m_collapse(*m_head, M_NOWAIT, STGE_MAXTXSEGS); 1083161235Syongari if (m == NULL) { 1084161235Syongari m_freem(*m_head); 1085161235Syongari *m_head = NULL; 1086160641Syongari return (ENOMEM); 1087160641Syongari } 1088161235Syongari *m_head = m; 1089160641Syongari error = bus_dmamap_load_mbuf_sg(sc->sc_cdata.stge_tx_tag, 1090161235Syongari txd->tx_dmamap, *m_head, txsegs, &nsegs, 0); 1091160641Syongari if (error != 0) { 1092161235Syongari m_freem(*m_head); 1093161235Syongari *m_head = NULL; 1094160641Syongari return (error); 1095160641Syongari } 1096160641Syongari } else if (error != 0) 1097160641Syongari return (error); 1098160641Syongari if (nsegs == 0) { 1099161235Syongari m_freem(*m_head); 1100161235Syongari *m_head = NULL; 1101160641Syongari return (EIO); 1102160641Syongari } 1103160641Syongari 1104161235Syongari m = *m_head; 1105160641Syongari csum_flags = 0; 1106160641Syongari if ((m->m_pkthdr.csum_flags & STGE_CSUM_FEATURES) != 0) { 1107160641Syongari if (m->m_pkthdr.csum_flags & CSUM_IP) 1108160641Syongari csum_flags |= TFD_IPChecksumEnable; 1109160641Syongari if (m->m_pkthdr.csum_flags & CSUM_TCP) 1110160641Syongari csum_flags |= TFD_TCPChecksumEnable; 1111160641Syongari else if (m->m_pkthdr.csum_flags & CSUM_UDP) 1112160641Syongari csum_flags |= TFD_UDPChecksumEnable; 1113160641Syongari } 1114160641Syongari 1115160641Syongari si = sc->sc_cdata.stge_tx_prod; 1116160641Syongari tfd = &sc->sc_rdata.stge_tx_ring[si]; 1117160641Syongari for (i = 0; i < nsegs; i++) 1118160641Syongari tfd->tfd_frags[i].frag_word0 = 1119160641Syongari htole64(FRAG_ADDR(txsegs[i].ds_addr) | 1120160641Syongari FRAG_LEN(txsegs[i].ds_len)); 1121160641Syongari sc->sc_cdata.stge_tx_cnt++; 1122160641Syongari 1123160641Syongari tfc = TFD_FrameId(si) | TFD_WordAlign(TFD_WordAlign_disable) | 1124160641Syongari TFD_FragCount(nsegs) | csum_flags; 1125160641Syongari if (sc->sc_cdata.stge_tx_cnt >= STGE_TX_HIWAT) 1126160641Syongari tfc |= TFD_TxDMAIndicate; 1127160641Syongari 1128160641Syongari /* Update producer index. */ 1129160641Syongari sc->sc_cdata.stge_tx_prod = (si + 1) % STGE_TX_RING_CNT; 1130160641Syongari 1131160641Syongari /* Check if we have a VLAN tag to insert. */ 1132162375Sandre if (m->m_flags & M_VLANTAG) 1133162375Sandre tfc |= (TFD_VLANTagInsert | TFD_VID(m->m_pkthdr.ether_vtag)); 1134160641Syongari tfd->tfd_control = htole64(tfc); 1135160641Syongari 1136160641Syongari /* Update Tx Queue. */ 1137160641Syongari STAILQ_REMOVE_HEAD(&sc->sc_cdata.stge_txfreeq, tx_q); 1138160641Syongari STAILQ_INSERT_TAIL(&sc->sc_cdata.stge_txbusyq, txd, tx_q); 1139160641Syongari txd->tx_m = m; 1140160641Syongari 1141160641Syongari /* Sync descriptors. */ 1142160641Syongari bus_dmamap_sync(sc->sc_cdata.stge_tx_tag, txd->tx_dmamap, 1143160641Syongari BUS_DMASYNC_PREWRITE); 1144160641Syongari bus_dmamap_sync(sc->sc_cdata.stge_tx_ring_tag, 1145160641Syongari sc->sc_cdata.stge_tx_ring_map, 1146160641Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1147160641Syongari 1148160641Syongari return (0); 1149160641Syongari} 1150160641Syongari 1151160641Syongari/* 1152160641Syongari * stge_start: [ifnet interface function] 1153160641Syongari * 1154160641Syongari * Start packet transmission on the interface. 1155160641Syongari */ 1156160641Syongaristatic void 1157160641Syongaristge_start(struct ifnet *ifp) 1158160641Syongari{ 1159160641Syongari struct stge_softc *sc; 1160160641Syongari 1161160641Syongari sc = ifp->if_softc; 1162160641Syongari STGE_LOCK(sc); 1163160641Syongari stge_start_locked(ifp); 1164160641Syongari STGE_UNLOCK(sc); 1165160641Syongari} 1166160641Syongari 1167160641Syongaristatic void 1168160641Syongaristge_start_locked(struct ifnet *ifp) 1169160641Syongari{ 1170160641Syongari struct stge_softc *sc; 1171160641Syongari struct mbuf *m_head; 1172160641Syongari int enq; 1173160641Syongari 1174160641Syongari sc = ifp->if_softc; 1175160641Syongari 1176160641Syongari STGE_LOCK_ASSERT(sc); 1177160641Syongari 1178160641Syongari if ((ifp->if_drv_flags & (IFF_DRV_RUNNING|IFF_DRV_OACTIVE)) != 1179169158Syongari IFF_DRV_RUNNING || sc->sc_link == 0) 1180160641Syongari return; 1181160641Syongari 1182160641Syongari for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) { 1183160641Syongari if (sc->sc_cdata.stge_tx_cnt >= STGE_TX_HIWAT) { 1184160641Syongari ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1185160641Syongari break; 1186160641Syongari } 1187160641Syongari 1188160641Syongari IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1189160641Syongari if (m_head == NULL) 1190160641Syongari break; 1191160641Syongari /* 1192160641Syongari * Pack the data into the transmit ring. If we 1193160641Syongari * don't have room, set the OACTIVE flag and wait 1194160641Syongari * for the NIC to drain the ring. 1195160641Syongari */ 1196160641Syongari if (stge_encap(sc, &m_head)) { 1197160641Syongari if (m_head == NULL) 1198160641Syongari break; 1199160641Syongari IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1200160641Syongari ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1201160641Syongari break; 1202160641Syongari } 1203160641Syongari 1204160641Syongari enq++; 1205160641Syongari /* 1206160641Syongari * If there's a BPF listener, bounce a copy of this frame 1207160641Syongari * to him. 1208160641Syongari */ 1209167190Scsjp ETHER_BPF_MTAP(ifp, m_head); 1210160641Syongari } 1211160641Syongari 1212160641Syongari if (enq > 0) { 1213160641Syongari /* Transmit */ 1214160641Syongari CSR_WRITE_4(sc, STGE_DMACtrl, DMAC_TxDMAPollNow); 1215160641Syongari 1216160641Syongari /* Set a timeout in case the chip goes out to lunch. */ 1217169157Syongari sc->sc_watchdog_timer = 5; 1218160641Syongari } 1219160641Syongari} 1220160641Syongari 1221160641Syongari/* 1222169157Syongari * stge_watchdog: 1223160641Syongari * 1224160641Syongari * Watchdog timer handler. 1225160641Syongari */ 1226160641Syongaristatic void 1227169157Syongaristge_watchdog(struct stge_softc *sc) 1228160641Syongari{ 1229169157Syongari struct ifnet *ifp; 1230160641Syongari 1231169157Syongari STGE_LOCK_ASSERT(sc); 1232160641Syongari 1233169157Syongari if (sc->sc_watchdog_timer == 0 || --sc->sc_watchdog_timer) 1234169157Syongari return; 1235169157Syongari 1236169157Syongari ifp = sc->sc_ifp; 1237160641Syongari if_printf(sc->sc_ifp, "device timeout\n"); 1238271837Sglebius if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1239212972Syongari ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1240160641Syongari stge_init_locked(sc); 1241169159Syongari if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1242169159Syongari stge_start_locked(ifp); 1243160641Syongari} 1244160641Syongari 1245160641Syongari/* 1246160641Syongari * stge_ioctl: [ifnet interface function] 1247160641Syongari * 1248160641Syongari * Handle control requests from the operator. 1249160641Syongari */ 1250160641Syongaristatic int 1251160641Syongaristge_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1252160641Syongari{ 1253160641Syongari struct stge_softc *sc; 1254160641Syongari struct ifreq *ifr; 1255160641Syongari struct mii_data *mii; 1256160641Syongari int error, mask; 1257160641Syongari 1258160641Syongari sc = ifp->if_softc; 1259160641Syongari ifr = (struct ifreq *)data; 1260160641Syongari error = 0; 1261160641Syongari switch (cmd) { 1262160641Syongari case SIOCSIFMTU: 1263160641Syongari if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > STGE_JUMBO_MTU) 1264160641Syongari error = EINVAL; 1265160641Syongari else if (ifp->if_mtu != ifr->ifr_mtu) { 1266160641Syongari ifp->if_mtu = ifr->ifr_mtu; 1267160641Syongari STGE_LOCK(sc); 1268212972Syongari if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1269212972Syongari ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1270212972Syongari stge_init_locked(sc); 1271212972Syongari } 1272160641Syongari STGE_UNLOCK(sc); 1273160641Syongari } 1274160641Syongari break; 1275160641Syongari case SIOCSIFFLAGS: 1276160641Syongari STGE_LOCK(sc); 1277160641Syongari if ((ifp->if_flags & IFF_UP) != 0) { 1278160641Syongari if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1279160641Syongari if (((ifp->if_flags ^ sc->sc_if_flags) 1280160641Syongari & IFF_PROMISC) != 0) 1281160641Syongari stge_set_filter(sc); 1282160641Syongari } else { 1283160641Syongari if (sc->sc_detach == 0) 1284160641Syongari stge_init_locked(sc); 1285160641Syongari } 1286160641Syongari } else { 1287160641Syongari if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1288160641Syongari stge_stop(sc); 1289160641Syongari } 1290160641Syongari sc->sc_if_flags = ifp->if_flags; 1291160641Syongari STGE_UNLOCK(sc); 1292160641Syongari break; 1293160641Syongari case SIOCADDMULTI: 1294160641Syongari case SIOCDELMULTI: 1295160641Syongari STGE_LOCK(sc); 1296160641Syongari if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1297160641Syongari stge_set_multi(sc); 1298160641Syongari STGE_UNLOCK(sc); 1299160641Syongari break; 1300160641Syongari case SIOCSIFMEDIA: 1301160641Syongari case SIOCGIFMEDIA: 1302160641Syongari mii = device_get_softc(sc->sc_miibus); 1303160641Syongari error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1304160641Syongari break; 1305160641Syongari case SIOCSIFCAP: 1306160641Syongari mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1307160641Syongari#ifdef DEVICE_POLLING 1308160641Syongari if ((mask & IFCAP_POLLING) != 0) { 1309160641Syongari if ((ifr->ifr_reqcap & IFCAP_POLLING) != 0) { 1310160641Syongari error = ether_poll_register(stge_poll, ifp); 1311160641Syongari if (error != 0) 1312160641Syongari break; 1313160641Syongari STGE_LOCK(sc); 1314160641Syongari CSR_WRITE_2(sc, STGE_IntEnable, 0); 1315160641Syongari ifp->if_capenable |= IFCAP_POLLING; 1316160641Syongari STGE_UNLOCK(sc); 1317160641Syongari } else { 1318160641Syongari error = ether_poll_deregister(ifp); 1319160641Syongari if (error != 0) 1320160641Syongari break; 1321160641Syongari STGE_LOCK(sc); 1322160641Syongari CSR_WRITE_2(sc, STGE_IntEnable, 1323160641Syongari sc->sc_IntEnable); 1324160641Syongari ifp->if_capenable &= ~IFCAP_POLLING; 1325160641Syongari STGE_UNLOCK(sc); 1326160641Syongari } 1327160641Syongari } 1328160641Syongari#endif 1329160641Syongari if ((mask & IFCAP_HWCSUM) != 0) { 1330160641Syongari ifp->if_capenable ^= IFCAP_HWCSUM; 1331160641Syongari if ((IFCAP_HWCSUM & ifp->if_capenable) != 0 && 1332160641Syongari (IFCAP_HWCSUM & ifp->if_capabilities) != 0) 1333160641Syongari ifp->if_hwassist = STGE_CSUM_FEATURES; 1334160641Syongari else 1335160641Syongari ifp->if_hwassist = 0; 1336160641Syongari } 1337175315Syongari if ((mask & IFCAP_WOL) != 0 && 1338175315Syongari (ifp->if_capabilities & IFCAP_WOL) != 0) { 1339175315Syongari if ((mask & IFCAP_WOL_MAGIC) != 0) 1340175315Syongari ifp->if_capenable ^= IFCAP_WOL_MAGIC; 1341175315Syongari } 1342160641Syongari if ((mask & IFCAP_VLAN_HWTAGGING) != 0) { 1343160641Syongari ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 1344160641Syongari if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1345160641Syongari STGE_LOCK(sc); 1346160641Syongari stge_vlan_setup(sc); 1347160641Syongari STGE_UNLOCK(sc); 1348160641Syongari } 1349160641Syongari } 1350160641Syongari VLAN_CAPABILITIES(ifp); 1351160641Syongari break; 1352160641Syongari default: 1353160641Syongari error = ether_ioctl(ifp, cmd, data); 1354160641Syongari break; 1355160641Syongari } 1356160641Syongari 1357160641Syongari return (error); 1358160641Syongari} 1359160641Syongari 1360160641Syongaristatic void 1361160641Syongaristge_link_task(void *arg, int pending) 1362160641Syongari{ 1363160641Syongari struct stge_softc *sc; 1364169158Syongari struct mii_data *mii; 1365160641Syongari uint32_t v, ac; 1366160641Syongari int i; 1367160641Syongari 1368160641Syongari sc = (struct stge_softc *)arg; 1369160641Syongari STGE_LOCK(sc); 1370169158Syongari 1371169158Syongari mii = device_get_softc(sc->sc_miibus); 1372169158Syongari if (mii->mii_media_status & IFM_ACTIVE) { 1373169158Syongari if (IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 1374169158Syongari sc->sc_link = 1; 1375169158Syongari } else 1376169158Syongari sc->sc_link = 0; 1377169158Syongari 1378169158Syongari sc->sc_MACCtrl = 0; 1379169158Syongari if (((mii->mii_media_active & IFM_GMASK) & IFM_FDX) != 0) 1380169158Syongari sc->sc_MACCtrl |= MC_DuplexSelect; 1381215297Smarius if (((mii->mii_media_active & IFM_GMASK) & IFM_ETH_RXPAUSE) != 0) 1382169158Syongari sc->sc_MACCtrl |= MC_RxFlowControlEnable; 1383215297Smarius if (((mii->mii_media_active & IFM_GMASK) & IFM_ETH_TXPAUSE) != 0) 1384169158Syongari sc->sc_MACCtrl |= MC_TxFlowControlEnable; 1385160641Syongari /* 1386160641Syongari * Update STGE_MACCtrl register depending on link status. 1387160641Syongari * (duplex, flow control etc) 1388160641Syongari */ 1389160641Syongari v = ac = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; 1390160641Syongari v &= ~(MC_DuplexSelect|MC_RxFlowControlEnable|MC_TxFlowControlEnable); 1391160641Syongari v |= sc->sc_MACCtrl; 1392160641Syongari CSR_WRITE_4(sc, STGE_MACCtrl, v); 1393160641Syongari if (((ac ^ sc->sc_MACCtrl) & MC_DuplexSelect) != 0) { 1394160641Syongari /* Duplex setting changed, reset Tx/Rx functions. */ 1395160641Syongari ac = CSR_READ_4(sc, STGE_AsicCtrl); 1396160641Syongari ac |= AC_TxReset | AC_RxReset; 1397160641Syongari CSR_WRITE_4(sc, STGE_AsicCtrl, ac); 1398160641Syongari for (i = 0; i < STGE_TIMEOUT; i++) { 1399160641Syongari DELAY(100); 1400160641Syongari if ((CSR_READ_4(sc, STGE_AsicCtrl) & AC_ResetBusy) == 0) 1401160641Syongari break; 1402160641Syongari } 1403160641Syongari if (i == STGE_TIMEOUT) 1404160641Syongari device_printf(sc->sc_dev, "reset failed to complete\n"); 1405160641Syongari } 1406160641Syongari STGE_UNLOCK(sc); 1407160641Syongari} 1408160641Syongari 1409160641Syongaristatic __inline int 1410160641Syongaristge_tx_error(struct stge_softc *sc) 1411160641Syongari{ 1412160641Syongari uint32_t txstat; 1413160641Syongari int error; 1414160641Syongari 1415160641Syongari for (error = 0;;) { 1416160641Syongari txstat = CSR_READ_4(sc, STGE_TxStatus); 1417160641Syongari if ((txstat & TS_TxComplete) == 0) 1418160641Syongari break; 1419160641Syongari /* Tx underrun */ 1420160641Syongari if ((txstat & TS_TxUnderrun) != 0) { 1421160641Syongari /* 1422160641Syongari * XXX 1423160641Syongari * There should be a more better way to recover 1424160641Syongari * from Tx underrun instead of a full reset. 1425160641Syongari */ 1426160641Syongari if (sc->sc_nerr++ < STGE_MAXERR) 1427160641Syongari device_printf(sc->sc_dev, "Tx underrun, " 1428160641Syongari "resetting...\n"); 1429160641Syongari if (sc->sc_nerr == STGE_MAXERR) 1430160641Syongari device_printf(sc->sc_dev, "too many errors; " 1431160641Syongari "not reporting any more\n"); 1432160641Syongari error = -1; 1433160641Syongari break; 1434160641Syongari } 1435160641Syongari /* Maximum/Late collisions, Re-enable Tx MAC. */ 1436160641Syongari if ((txstat & (TS_MaxCollisions|TS_LateCollision)) != 0) 1437160641Syongari CSR_WRITE_4(sc, STGE_MACCtrl, 1438160641Syongari (CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK) | 1439160641Syongari MC_TxEnable); 1440160641Syongari } 1441160641Syongari 1442160641Syongari return (error); 1443160641Syongari} 1444160641Syongari 1445160641Syongari/* 1446160641Syongari * stge_intr: 1447160641Syongari * 1448160641Syongari * Interrupt service routine. 1449160641Syongari */ 1450160641Syongaristatic void 1451160641Syongaristge_intr(void *arg) 1452160641Syongari{ 1453160641Syongari struct stge_softc *sc; 1454160641Syongari struct ifnet *ifp; 1455160641Syongari int reinit; 1456160641Syongari uint16_t status; 1457160641Syongari 1458160641Syongari sc = (struct stge_softc *)arg; 1459160641Syongari ifp = sc->sc_ifp; 1460160641Syongari 1461160641Syongari STGE_LOCK(sc); 1462160641Syongari 1463160641Syongari#ifdef DEVICE_POLLING 1464160641Syongari if ((ifp->if_capenable & IFCAP_POLLING) != 0) 1465160641Syongari goto done_locked; 1466160641Syongari#endif 1467160641Syongari status = CSR_READ_2(sc, STGE_IntStatus); 1468160641Syongari if (sc->sc_suspended || (status & IS_InterruptStatus) == 0) 1469160641Syongari goto done_locked; 1470160641Syongari 1471160641Syongari /* Disable interrupts. */ 1472160641Syongari for (reinit = 0;;) { 1473160641Syongari status = CSR_READ_2(sc, STGE_IntStatusAck); 1474160641Syongari status &= sc->sc_IntEnable; 1475160641Syongari if (status == 0) 1476160641Syongari break; 1477160641Syongari /* Host interface errors. */ 1478160641Syongari if ((status & IS_HostError) != 0) { 1479160641Syongari device_printf(sc->sc_dev, 1480160641Syongari "Host interface error, resetting...\n"); 1481160641Syongari reinit = 1; 1482160641Syongari goto force_init; 1483160641Syongari } 1484160641Syongari 1485160641Syongari /* Receive interrupts. */ 1486160641Syongari if ((status & IS_RxDMAComplete) != 0) { 1487160641Syongari stge_rxeof(sc); 1488160641Syongari if ((status & IS_RFDListEnd) != 0) 1489160641Syongari CSR_WRITE_4(sc, STGE_DMACtrl, 1490160641Syongari DMAC_RxDMAPollNow); 1491160641Syongari } 1492160641Syongari 1493160641Syongari /* Transmit interrupts. */ 1494160641Syongari if ((status & (IS_TxDMAComplete | IS_TxComplete)) != 0) 1495160641Syongari stge_txeof(sc); 1496160641Syongari 1497160641Syongari /* Transmission errors.*/ 1498160641Syongari if ((status & IS_TxComplete) != 0) { 1499160641Syongari if ((reinit = stge_tx_error(sc)) != 0) 1500160641Syongari break; 1501160641Syongari } 1502160641Syongari } 1503160641Syongari 1504160641Syongariforce_init: 1505212972Syongari if (reinit != 0) { 1506212972Syongari ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1507160641Syongari stge_init_locked(sc); 1508212972Syongari } 1509160641Syongari 1510160641Syongari /* Re-enable interrupts. */ 1511160641Syongari CSR_WRITE_2(sc, STGE_IntEnable, sc->sc_IntEnable); 1512160641Syongari 1513160641Syongari /* Try to get more packets going. */ 1514160641Syongari if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1515160641Syongari stge_start_locked(ifp); 1516160641Syongari 1517160641Syongaridone_locked: 1518160641Syongari STGE_UNLOCK(sc); 1519160641Syongari} 1520160641Syongari 1521160641Syongari/* 1522160641Syongari * stge_txeof: 1523160641Syongari * 1524160641Syongari * Helper; handle transmit interrupts. 1525160641Syongari */ 1526160641Syongaristatic void 1527160641Syongaristge_txeof(struct stge_softc *sc) 1528160641Syongari{ 1529160641Syongari struct ifnet *ifp; 1530160641Syongari struct stge_txdesc *txd; 1531160641Syongari uint64_t control; 1532160641Syongari int cons; 1533160641Syongari 1534160641Syongari STGE_LOCK_ASSERT(sc); 1535160641Syongari 1536160641Syongari ifp = sc->sc_ifp; 1537160641Syongari 1538160641Syongari txd = STAILQ_FIRST(&sc->sc_cdata.stge_txbusyq); 1539160641Syongari if (txd == NULL) 1540160641Syongari return; 1541160641Syongari bus_dmamap_sync(sc->sc_cdata.stge_tx_ring_tag, 1542160641Syongari sc->sc_cdata.stge_tx_ring_map, BUS_DMASYNC_POSTREAD); 1543160641Syongari 1544160641Syongari /* 1545160641Syongari * Go through our Tx list and free mbufs for those 1546160641Syongari * frames which have been transmitted. 1547160641Syongari */ 1548160641Syongari for (cons = sc->sc_cdata.stge_tx_cons;; 1549160641Syongari cons = (cons + 1) % STGE_TX_RING_CNT) { 1550160641Syongari if (sc->sc_cdata.stge_tx_cnt <= 0) 1551160641Syongari break; 1552160641Syongari control = le64toh(sc->sc_rdata.stge_tx_ring[cons].tfd_control); 1553160641Syongari if ((control & TFD_TFDDone) == 0) 1554160641Syongari break; 1555160641Syongari sc->sc_cdata.stge_tx_cnt--; 1556160641Syongari ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1557160641Syongari 1558160641Syongari bus_dmamap_sync(sc->sc_cdata.stge_tx_tag, txd->tx_dmamap, 1559160641Syongari BUS_DMASYNC_POSTWRITE); 1560160641Syongari bus_dmamap_unload(sc->sc_cdata.stge_tx_tag, txd->tx_dmamap); 1561160641Syongari 1562160641Syongari /* Output counter is updated with statistics register */ 1563160641Syongari m_freem(txd->tx_m); 1564160641Syongari txd->tx_m = NULL; 1565160641Syongari STAILQ_REMOVE_HEAD(&sc->sc_cdata.stge_txbusyq, tx_q); 1566160641Syongari STAILQ_INSERT_TAIL(&sc->sc_cdata.stge_txfreeq, txd, tx_q); 1567160641Syongari txd = STAILQ_FIRST(&sc->sc_cdata.stge_txbusyq); 1568160641Syongari } 1569160641Syongari sc->sc_cdata.stge_tx_cons = cons; 1570160641Syongari if (sc->sc_cdata.stge_tx_cnt == 0) 1571169157Syongari sc->sc_watchdog_timer = 0; 1572160641Syongari 1573160641Syongari bus_dmamap_sync(sc->sc_cdata.stge_tx_ring_tag, 1574160641Syongari sc->sc_cdata.stge_tx_ring_map, 1575160641Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1576160641Syongari} 1577160641Syongari 1578160641Syongaristatic __inline void 1579160641Syongaristge_discard_rxbuf(struct stge_softc *sc, int idx) 1580160641Syongari{ 1581160641Syongari struct stge_rfd *rfd; 1582160641Syongari 1583160641Syongari rfd = &sc->sc_rdata.stge_rx_ring[idx]; 1584160641Syongari rfd->rfd_status = 0; 1585160641Syongari} 1586160641Syongari 1587160641Syongari#ifndef __NO_STRICT_ALIGNMENT 1588160641Syongari/* 1589160641Syongari * It seems that TC9021's DMA engine has alignment restrictions in 1590160641Syongari * DMA scatter operations. The first DMA segment has no address 1591160641Syongari * alignment restrictins but the rest should be aligned on 4(?) bytes 1592160641Syongari * boundary. Otherwise it would corrupt random memory. Since we don't 1593160641Syongari * know which one is used for the first segment in advance we simply 1594160641Syongari * don't align at all. 1595160641Syongari * To avoid copying over an entire frame to align, we allocate a new 1596160641Syongari * mbuf and copy ethernet header to the new mbuf. The new mbuf is 1597160641Syongari * prepended into the existing mbuf chain. 1598160641Syongari */ 1599160641Syongaristatic __inline struct mbuf * 1600160641Syongaristge_fixup_rx(struct stge_softc *sc, struct mbuf *m) 1601160641Syongari{ 1602160641Syongari struct mbuf *n; 1603160641Syongari 1604160641Syongari n = NULL; 1605160641Syongari if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) { 1606160641Syongari bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 1607160641Syongari m->m_data += ETHER_HDR_LEN; 1608160641Syongari n = m; 1609160641Syongari } else { 1610243857Sglebius MGETHDR(n, M_NOWAIT, MT_DATA); 1611160641Syongari if (n != NULL) { 1612160641Syongari bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 1613160641Syongari m->m_data += ETHER_HDR_LEN; 1614160641Syongari m->m_len -= ETHER_HDR_LEN; 1615160641Syongari n->m_len = ETHER_HDR_LEN; 1616160641Syongari M_MOVE_PKTHDR(n, m); 1617160641Syongari n->m_next = m; 1618160641Syongari } else 1619160641Syongari m_freem(m); 1620160641Syongari } 1621160641Syongari 1622160641Syongari return (n); 1623160641Syongari} 1624160641Syongari#endif 1625160641Syongari 1626160641Syongari/* 1627160641Syongari * stge_rxeof: 1628160641Syongari * 1629160641Syongari * Helper; handle receive interrupts. 1630160641Syongari */ 1631193096Sattiliostatic int 1632160641Syongaristge_rxeof(struct stge_softc *sc) 1633160641Syongari{ 1634160641Syongari struct ifnet *ifp; 1635160641Syongari struct stge_rxdesc *rxd; 1636160641Syongari struct mbuf *mp, *m; 1637160641Syongari uint64_t status64; 1638160641Syongari uint32_t status; 1639193096Sattilio int cons, prog, rx_npkts; 1640160641Syongari 1641160641Syongari STGE_LOCK_ASSERT(sc); 1642160641Syongari 1643193096Sattilio rx_npkts = 0; 1644160641Syongari ifp = sc->sc_ifp; 1645160641Syongari 1646160641Syongari bus_dmamap_sync(sc->sc_cdata.stge_rx_ring_tag, 1647160641Syongari sc->sc_cdata.stge_rx_ring_map, BUS_DMASYNC_POSTREAD); 1648160641Syongari 1649160641Syongari prog = 0; 1650160641Syongari for (cons = sc->sc_cdata.stge_rx_cons; prog < STGE_RX_RING_CNT; 1651160641Syongari prog++, cons = (cons + 1) % STGE_RX_RING_CNT) { 1652160641Syongari status64 = le64toh(sc->sc_rdata.stge_rx_ring[cons].rfd_status); 1653160641Syongari status = RFD_RxStatus(status64); 1654160641Syongari if ((status & RFD_RFDDone) == 0) 1655160641Syongari break; 1656160641Syongari#ifdef DEVICE_POLLING 1657160641Syongari if (ifp->if_capenable & IFCAP_POLLING) { 1658160641Syongari if (sc->sc_cdata.stge_rxcycles <= 0) 1659160641Syongari break; 1660160641Syongari sc->sc_cdata.stge_rxcycles--; 1661160641Syongari } 1662160641Syongari#endif 1663160641Syongari prog++; 1664160641Syongari rxd = &sc->sc_cdata.stge_rxdesc[cons]; 1665160641Syongari mp = rxd->rx_m; 1666160641Syongari 1667160641Syongari /* 1668160641Syongari * If the packet had an error, drop it. Note we count 1669160641Syongari * the error later in the periodic stats update. 1670160641Syongari */ 1671160641Syongari if ((status & RFD_FrameEnd) != 0 && (status & 1672160641Syongari (RFD_RxFIFOOverrun | RFD_RxRuntFrame | 1673160641Syongari RFD_RxAlignmentError | RFD_RxFCSError | 1674160641Syongari RFD_RxLengthError)) != 0) { 1675160641Syongari stge_discard_rxbuf(sc, cons); 1676160641Syongari if (sc->sc_cdata.stge_rxhead != NULL) { 1677160641Syongari m_freem(sc->sc_cdata.stge_rxhead); 1678160641Syongari STGE_RXCHAIN_RESET(sc); 1679160641Syongari } 1680160641Syongari continue; 1681160641Syongari } 1682160641Syongari /* 1683160641Syongari * Add a new receive buffer to the ring. 1684160641Syongari */ 1685160641Syongari if (stge_newbuf(sc, cons) != 0) { 1686271837Sglebius if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 1687160641Syongari stge_discard_rxbuf(sc, cons); 1688160641Syongari if (sc->sc_cdata.stge_rxhead != NULL) { 1689160641Syongari m_freem(sc->sc_cdata.stge_rxhead); 1690160641Syongari STGE_RXCHAIN_RESET(sc); 1691160641Syongari } 1692160641Syongari continue; 1693160641Syongari } 1694160641Syongari 1695160641Syongari if ((status & RFD_FrameEnd) != 0) 1696160641Syongari mp->m_len = RFD_RxDMAFrameLen(status) - 1697160641Syongari sc->sc_cdata.stge_rxlen; 1698160641Syongari sc->sc_cdata.stge_rxlen += mp->m_len; 1699160641Syongari 1700160641Syongari /* Chain mbufs. */ 1701160641Syongari if (sc->sc_cdata.stge_rxhead == NULL) { 1702160641Syongari sc->sc_cdata.stge_rxhead = mp; 1703160641Syongari sc->sc_cdata.stge_rxtail = mp; 1704160641Syongari } else { 1705160641Syongari mp->m_flags &= ~M_PKTHDR; 1706160641Syongari sc->sc_cdata.stge_rxtail->m_next = mp; 1707160641Syongari sc->sc_cdata.stge_rxtail = mp; 1708160641Syongari } 1709160641Syongari 1710160641Syongari if ((status & RFD_FrameEnd) != 0) { 1711160641Syongari m = sc->sc_cdata.stge_rxhead; 1712160641Syongari m->m_pkthdr.rcvif = ifp; 1713160641Syongari m->m_pkthdr.len = sc->sc_cdata.stge_rxlen; 1714160641Syongari 1715160641Syongari if (m->m_pkthdr.len > sc->sc_if_framesize) { 1716160641Syongari m_freem(m); 1717160641Syongari STGE_RXCHAIN_RESET(sc); 1718160641Syongari continue; 1719160641Syongari } 1720160641Syongari /* 1721160641Syongari * Set the incoming checksum information for 1722160641Syongari * the packet. 1723160641Syongari */ 1724160641Syongari if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) { 1725160641Syongari if ((status & RFD_IPDetected) != 0) { 1726160641Syongari m->m_pkthdr.csum_flags |= 1727160641Syongari CSUM_IP_CHECKED; 1728160641Syongari if ((status & RFD_IPError) == 0) 1729160641Syongari m->m_pkthdr.csum_flags |= 1730160641Syongari CSUM_IP_VALID; 1731160641Syongari } 1732160641Syongari if (((status & RFD_TCPDetected) != 0 && 1733160641Syongari (status & RFD_TCPError) == 0) || 1734160641Syongari ((status & RFD_UDPDetected) != 0 && 1735160641Syongari (status & RFD_UDPError) == 0)) { 1736160641Syongari m->m_pkthdr.csum_flags |= 1737160641Syongari (CSUM_DATA_VALID | CSUM_PSEUDO_HDR); 1738160641Syongari m->m_pkthdr.csum_data = 0xffff; 1739160641Syongari } 1740160641Syongari } 1741160641Syongari 1742160641Syongari#ifndef __NO_STRICT_ALIGNMENT 1743160641Syongari if (sc->sc_if_framesize > (MCLBYTES - ETHER_ALIGN)) { 1744160641Syongari if ((m = stge_fixup_rx(sc, m)) == NULL) { 1745160641Syongari STGE_RXCHAIN_RESET(sc); 1746160641Syongari continue; 1747160641Syongari } 1748160641Syongari } 1749160641Syongari#endif 1750160641Syongari /* Check for VLAN tagged packets. */ 1751160641Syongari if ((status & RFD_VLANDetected) != 0 && 1752162375Sandre (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) { 1753162375Sandre m->m_pkthdr.ether_vtag = RFD_TCI(status64); 1754162375Sandre m->m_flags |= M_VLANTAG; 1755162375Sandre } 1756160641Syongari 1757160641Syongari STGE_UNLOCK(sc); 1758160641Syongari /* Pass it on. */ 1759160641Syongari (*ifp->if_input)(ifp, m); 1760160641Syongari STGE_LOCK(sc); 1761193096Sattilio rx_npkts++; 1762160641Syongari 1763160641Syongari STGE_RXCHAIN_RESET(sc); 1764160641Syongari } 1765160641Syongari } 1766160641Syongari 1767160641Syongari if (prog > 0) { 1768160641Syongari /* Update the consumer index. */ 1769160641Syongari sc->sc_cdata.stge_rx_cons = cons; 1770160641Syongari bus_dmamap_sync(sc->sc_cdata.stge_rx_ring_tag, 1771160641Syongari sc->sc_cdata.stge_rx_ring_map, 1772160641Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1773160641Syongari } 1774193096Sattilio return (rx_npkts); 1775160641Syongari} 1776160641Syongari 1777160641Syongari#ifdef DEVICE_POLLING 1778193096Sattiliostatic int 1779160641Syongaristge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1780160641Syongari{ 1781160641Syongari struct stge_softc *sc; 1782160641Syongari uint16_t status; 1783193096Sattilio int rx_npkts; 1784160641Syongari 1785193096Sattilio rx_npkts = 0; 1786160641Syongari sc = ifp->if_softc; 1787160641Syongari STGE_LOCK(sc); 1788160641Syongari if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1789160641Syongari STGE_UNLOCK(sc); 1790193096Sattilio return (rx_npkts); 1791160641Syongari } 1792160641Syongari 1793160641Syongari sc->sc_cdata.stge_rxcycles = count; 1794193096Sattilio rx_npkts = stge_rxeof(sc); 1795160641Syongari stge_txeof(sc); 1796160641Syongari 1797160641Syongari if (cmd == POLL_AND_CHECK_STATUS) { 1798160641Syongari status = CSR_READ_2(sc, STGE_IntStatus); 1799160641Syongari status &= sc->sc_IntEnable; 1800160641Syongari if (status != 0) { 1801160641Syongari if ((status & IS_HostError) != 0) { 1802160641Syongari device_printf(sc->sc_dev, 1803160641Syongari "Host interface error, resetting...\n"); 1804212972Syongari ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1805160641Syongari stge_init_locked(sc); 1806160641Syongari } 1807160641Syongari if ((status & IS_TxComplete) != 0) { 1808212972Syongari if (stge_tx_error(sc) != 0) { 1809212972Syongari ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1810160641Syongari stge_init_locked(sc); 1811212972Syongari } 1812160641Syongari } 1813160641Syongari } 1814160641Syongari 1815160641Syongari } 1816160641Syongari 1817160641Syongari if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1818160641Syongari stge_start_locked(ifp); 1819160641Syongari 1820160641Syongari STGE_UNLOCK(sc); 1821193096Sattilio return (rx_npkts); 1822160641Syongari} 1823160641Syongari#endif /* DEVICE_POLLING */ 1824160641Syongari 1825160641Syongari/* 1826160641Syongari * stge_tick: 1827160641Syongari * 1828160641Syongari * One second timer, used to tick the MII. 1829160641Syongari */ 1830160641Syongaristatic void 1831160641Syongaristge_tick(void *arg) 1832160641Syongari{ 1833160641Syongari struct stge_softc *sc; 1834160641Syongari struct mii_data *mii; 1835160641Syongari 1836160641Syongari sc = (struct stge_softc *)arg; 1837160641Syongari 1838160641Syongari STGE_LOCK_ASSERT(sc); 1839160641Syongari 1840160641Syongari mii = device_get_softc(sc->sc_miibus); 1841160641Syongari mii_tick(mii); 1842160641Syongari 1843160641Syongari /* Update statistics counters. */ 1844160641Syongari stge_stats_update(sc); 1845160641Syongari 1846160641Syongari /* 1847160641Syongari * Relcaim any pending Tx descriptors to release mbufs in a 1848160641Syongari * timely manner as we don't generate Tx completion interrupts 1849160641Syongari * for every frame. This limits the delay to a maximum of one 1850160641Syongari * second. 1851160641Syongari */ 1852160641Syongari if (sc->sc_cdata.stge_tx_cnt != 0) 1853160641Syongari stge_txeof(sc); 1854160641Syongari 1855169157Syongari stge_watchdog(sc); 1856169157Syongari 1857160641Syongari callout_reset(&sc->sc_tick_ch, hz, stge_tick, sc); 1858160641Syongari} 1859160641Syongari 1860160641Syongari/* 1861160641Syongari * stge_stats_update: 1862160641Syongari * 1863160641Syongari * Read the TC9021 statistics counters. 1864160641Syongari */ 1865160641Syongaristatic void 1866160641Syongaristge_stats_update(struct stge_softc *sc) 1867160641Syongari{ 1868160641Syongari struct ifnet *ifp; 1869160641Syongari 1870160641Syongari STGE_LOCK_ASSERT(sc); 1871160641Syongari 1872160641Syongari ifp = sc->sc_ifp; 1873160641Syongari 1874160641Syongari CSR_READ_4(sc,STGE_OctetRcvOk); 1875160641Syongari 1876271837Sglebius if_inc_counter(ifp, IFCOUNTER_IPACKETS, CSR_READ_4(sc, STGE_FramesRcvdOk)); 1877160641Syongari 1878271837Sglebius if_inc_counter(ifp, IFCOUNTER_IERRORS, CSR_READ_2(sc, STGE_FramesLostRxErrors)); 1879160641Syongari 1880160641Syongari CSR_READ_4(sc, STGE_OctetXmtdOk); 1881160641Syongari 1882271837Sglebius if_inc_counter(ifp, IFCOUNTER_OPACKETS, CSR_READ_4(sc, STGE_FramesXmtdOk)); 1883160641Syongari 1884271837Sglebius if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1885160641Syongari CSR_READ_4(sc, STGE_LateCollisions) + 1886160641Syongari CSR_READ_4(sc, STGE_MultiColFrames) + 1887271837Sglebius CSR_READ_4(sc, STGE_SingleColFrames)); 1888160641Syongari 1889271837Sglebius if_inc_counter(ifp, IFCOUNTER_OERRORS, 1890160641Syongari CSR_READ_2(sc, STGE_FramesAbortXSColls) + 1891271837Sglebius CSR_READ_2(sc, STGE_FramesWEXDeferal)); 1892160641Syongari} 1893160641Syongari 1894160641Syongari/* 1895160641Syongari * stge_reset: 1896160641Syongari * 1897160641Syongari * Perform a soft reset on the TC9021. 1898160641Syongari */ 1899160641Syongaristatic void 1900160641Syongaristge_reset(struct stge_softc *sc, uint32_t how) 1901160641Syongari{ 1902160641Syongari uint32_t ac; 1903160641Syongari uint8_t v; 1904160641Syongari int i, dv; 1905160641Syongari 1906160641Syongari STGE_LOCK_ASSERT(sc); 1907160641Syongari 1908160641Syongari dv = 5000; 1909160641Syongari ac = CSR_READ_4(sc, STGE_AsicCtrl); 1910160641Syongari switch (how) { 1911160641Syongari case STGE_RESET_TX: 1912160641Syongari ac |= AC_TxReset | AC_FIFO; 1913160641Syongari dv = 100; 1914160641Syongari break; 1915160641Syongari case STGE_RESET_RX: 1916160641Syongari ac |= AC_RxReset | AC_FIFO; 1917160641Syongari dv = 100; 1918160641Syongari break; 1919160641Syongari case STGE_RESET_FULL: 1920160641Syongari default: 1921160641Syongari /* 1922160641Syongari * Only assert RstOut if we're fiber. We need GMII clocks 1923160641Syongari * to be present in order for the reset to complete on fiber 1924160641Syongari * cards. 1925160641Syongari */ 1926160641Syongari ac |= AC_GlobalReset | AC_RxReset | AC_TxReset | 1927160641Syongari AC_DMA | AC_FIFO | AC_Network | AC_Host | AC_AutoInit | 1928160641Syongari (sc->sc_usefiber ? AC_RstOut : 0); 1929160641Syongari break; 1930160641Syongari } 1931160641Syongari 1932160641Syongari CSR_WRITE_4(sc, STGE_AsicCtrl, ac); 1933160641Syongari 1934160641Syongari /* Account for reset problem at 10Mbps. */ 1935160641Syongari DELAY(dv); 1936160641Syongari 1937160641Syongari for (i = 0; i < STGE_TIMEOUT; i++) { 1938160641Syongari if ((CSR_READ_4(sc, STGE_AsicCtrl) & AC_ResetBusy) == 0) 1939160641Syongari break; 1940160641Syongari DELAY(dv); 1941160641Syongari } 1942160641Syongari 1943160641Syongari if (i == STGE_TIMEOUT) 1944160641Syongari device_printf(sc->sc_dev, "reset failed to complete\n"); 1945160641Syongari 1946160641Syongari /* Set LED, from Linux IPG driver. */ 1947160641Syongari ac = CSR_READ_4(sc, STGE_AsicCtrl); 1948160641Syongari ac &= ~(AC_LEDMode | AC_LEDSpeed | AC_LEDModeBit1); 1949160641Syongari if ((sc->sc_led & 0x01) != 0) 1950160641Syongari ac |= AC_LEDMode; 1951160641Syongari if ((sc->sc_led & 0x03) != 0) 1952160641Syongari ac |= AC_LEDModeBit1; 1953160641Syongari if ((sc->sc_led & 0x08) != 0) 1954160641Syongari ac |= AC_LEDSpeed; 1955160641Syongari CSR_WRITE_4(sc, STGE_AsicCtrl, ac); 1956160641Syongari 1957160641Syongari /* Set PHY, from Linux IPG driver */ 1958160641Syongari v = CSR_READ_1(sc, STGE_PhySet); 1959160641Syongari v &= ~(PS_MemLenb9b | PS_MemLen | PS_NonCompdet); 1960160641Syongari v |= ((sc->sc_led & 0x70) >> 4); 1961160641Syongari CSR_WRITE_1(sc, STGE_PhySet, v); 1962160641Syongari} 1963160641Syongari 1964160641Syongari/* 1965160641Syongari * stge_init: [ ifnet interface function ] 1966160641Syongari * 1967160641Syongari * Initialize the interface. 1968160641Syongari */ 1969160641Syongaristatic void 1970160641Syongaristge_init(void *xsc) 1971160641Syongari{ 1972160641Syongari struct stge_softc *sc; 1973160641Syongari 1974160641Syongari sc = (struct stge_softc *)xsc; 1975160641Syongari STGE_LOCK(sc); 1976160641Syongari stge_init_locked(sc); 1977160641Syongari STGE_UNLOCK(sc); 1978160641Syongari} 1979160641Syongari 1980160641Syongaristatic void 1981160641Syongaristge_init_locked(struct stge_softc *sc) 1982160641Syongari{ 1983160641Syongari struct ifnet *ifp; 1984160641Syongari struct mii_data *mii; 1985160641Syongari uint16_t eaddr[3]; 1986160641Syongari uint32_t v; 1987160641Syongari int error; 1988160641Syongari 1989160641Syongari STGE_LOCK_ASSERT(sc); 1990160641Syongari 1991160641Syongari ifp = sc->sc_ifp; 1992212972Syongari if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1993212972Syongari return; 1994160641Syongari mii = device_get_softc(sc->sc_miibus); 1995160641Syongari 1996160641Syongari /* 1997160641Syongari * Cancel any pending I/O. 1998160641Syongari */ 1999160641Syongari stge_stop(sc); 2000160641Syongari 2001175315Syongari /* 2002175315Syongari * Reset the chip to a known state. 2003175315Syongari */ 2004175315Syongari stge_reset(sc, STGE_RESET_FULL); 2005175315Syongari 2006160641Syongari /* Init descriptors. */ 2007160641Syongari error = stge_init_rx_ring(sc); 2008160641Syongari if (error != 0) { 2009160641Syongari device_printf(sc->sc_dev, 2010160641Syongari "initialization failed: no memory for rx buffers\n"); 2011160641Syongari stge_stop(sc); 2012160641Syongari goto out; 2013160641Syongari } 2014160641Syongari stge_init_tx_ring(sc); 2015160641Syongari 2016160641Syongari /* Set the station address. */ 2017160641Syongari bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); 2018160641Syongari CSR_WRITE_2(sc, STGE_StationAddress0, htole16(eaddr[0])); 2019160641Syongari CSR_WRITE_2(sc, STGE_StationAddress1, htole16(eaddr[1])); 2020160641Syongari CSR_WRITE_2(sc, STGE_StationAddress2, htole16(eaddr[2])); 2021160641Syongari 2022160641Syongari /* 2023160641Syongari * Set the statistics masks. Disable all the RMON stats, 2024160641Syongari * and disable selected stats in the non-RMON stats registers. 2025160641Syongari */ 2026160641Syongari CSR_WRITE_4(sc, STGE_RMONStatisticsMask, 0xffffffff); 2027160641Syongari CSR_WRITE_4(sc, STGE_StatisticsMask, 2028160641Syongari (1U << 1) | (1U << 2) | (1U << 3) | (1U << 4) | (1U << 5) | 2029160641Syongari (1U << 6) | (1U << 7) | (1U << 8) | (1U << 9) | (1U << 10) | 2030160641Syongari (1U << 13) | (1U << 14) | (1U << 15) | (1U << 19) | (1U << 20) | 2031160641Syongari (1U << 21)); 2032160641Syongari 2033160641Syongari /* Set up the receive filter. */ 2034160641Syongari stge_set_filter(sc); 2035160641Syongari /* Program multicast filter. */ 2036160641Syongari stge_set_multi(sc); 2037160641Syongari 2038160641Syongari /* 2039160641Syongari * Give the transmit and receive ring to the chip. 2040160641Syongari */ 2041160641Syongari CSR_WRITE_4(sc, STGE_TFDListPtrHi, 2042160641Syongari STGE_ADDR_HI(STGE_TX_RING_ADDR(sc, 0))); 2043160641Syongari CSR_WRITE_4(sc, STGE_TFDListPtrLo, 2044160641Syongari STGE_ADDR_LO(STGE_TX_RING_ADDR(sc, 0))); 2045160641Syongari 2046160641Syongari CSR_WRITE_4(sc, STGE_RFDListPtrHi, 2047160641Syongari STGE_ADDR_HI(STGE_RX_RING_ADDR(sc, 0))); 2048160641Syongari CSR_WRITE_4(sc, STGE_RFDListPtrLo, 2049160641Syongari STGE_ADDR_LO(STGE_RX_RING_ADDR(sc, 0))); 2050160641Syongari 2051160641Syongari /* 2052160641Syongari * Initialize the Tx auto-poll period. It's OK to make this number 2053160641Syongari * large (255 is the max, but we use 127) -- we explicitly kick the 2054160641Syongari * transmit engine when there's actually a packet. 2055160641Syongari */ 2056160641Syongari CSR_WRITE_1(sc, STGE_TxDMAPollPeriod, 127); 2057160641Syongari 2058160641Syongari /* ..and the Rx auto-poll period. */ 2059160641Syongari CSR_WRITE_1(sc, STGE_RxDMAPollPeriod, 1); 2060160641Syongari 2061160641Syongari /* Initialize the Tx start threshold. */ 2062160641Syongari CSR_WRITE_2(sc, STGE_TxStartThresh, sc->sc_txthresh); 2063160641Syongari 2064160641Syongari /* Rx DMA thresholds, from Linux */ 2065160641Syongari CSR_WRITE_1(sc, STGE_RxDMABurstThresh, 0x30); 2066160641Syongari CSR_WRITE_1(sc, STGE_RxDMAUrgentThresh, 0x30); 2067160641Syongari 2068160641Syongari /* Rx early threhold, from Linux */ 2069160641Syongari CSR_WRITE_2(sc, STGE_RxEarlyThresh, 0x7ff); 2070160641Syongari 2071160641Syongari /* Tx DMA thresholds, from Linux */ 2072160641Syongari CSR_WRITE_1(sc, STGE_TxDMABurstThresh, 0x30); 2073160641Syongari CSR_WRITE_1(sc, STGE_TxDMAUrgentThresh, 0x04); 2074160641Syongari 2075160641Syongari /* 2076160641Syongari * Initialize the Rx DMA interrupt control register. We 2077160641Syongari * request an interrupt after every incoming packet, but 2078160641Syongari * defer it for sc_rxint_dmawait us. When the number of 2079160641Syongari * interrupts pending reaches STGE_RXINT_NFRAME, we stop 2080160641Syongari * deferring the interrupt, and signal it immediately. 2081160641Syongari */ 2082160641Syongari CSR_WRITE_4(sc, STGE_RxDMAIntCtrl, 2083160641Syongari RDIC_RxFrameCount(sc->sc_rxint_nframe) | 2084160641Syongari RDIC_RxDMAWaitTime(STGE_RXINT_USECS2TICK(sc->sc_rxint_dmawait))); 2085160641Syongari 2086160641Syongari /* 2087160641Syongari * Initialize the interrupt mask. 2088160641Syongari */ 2089160641Syongari sc->sc_IntEnable = IS_HostError | IS_TxComplete | 2090160641Syongari IS_TxDMAComplete | IS_RxDMAComplete | IS_RFDListEnd; 2091160641Syongari#ifdef DEVICE_POLLING 2092160641Syongari /* Disable interrupts if we are polling. */ 2093160641Syongari if ((ifp->if_capenable & IFCAP_POLLING) != 0) 2094160641Syongari CSR_WRITE_2(sc, STGE_IntEnable, 0); 2095160641Syongari else 2096160641Syongari#endif 2097160641Syongari CSR_WRITE_2(sc, STGE_IntEnable, sc->sc_IntEnable); 2098160641Syongari 2099160641Syongari /* 2100160641Syongari * Configure the DMA engine. 2101160641Syongari * XXX Should auto-tune TxBurstLimit. 2102160641Syongari */ 2103160641Syongari CSR_WRITE_4(sc, STGE_DMACtrl, sc->sc_DMACtrl | DMAC_TxBurstLimit(3)); 2104160641Syongari 2105160641Syongari /* 2106160641Syongari * Send a PAUSE frame when we reach 29,696 bytes in the Rx 2107160641Syongari * FIFO, and send an un-PAUSE frame when we reach 3056 bytes 2108160641Syongari * in the Rx FIFO. 2109160641Syongari */ 2110160641Syongari CSR_WRITE_2(sc, STGE_FlowOnTresh, 29696 / 16); 2111160641Syongari CSR_WRITE_2(sc, STGE_FlowOffThresh, 3056 / 16); 2112160641Syongari 2113160641Syongari /* 2114160641Syongari * Set the maximum frame size. 2115160641Syongari */ 2116160641Syongari sc->sc_if_framesize = ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 2117160641Syongari CSR_WRITE_2(sc, STGE_MaxFrameSize, sc->sc_if_framesize); 2118160641Syongari 2119160641Syongari /* 2120160641Syongari * Initialize MacCtrl -- do it before setting the media, 2121160641Syongari * as setting the media will actually program the register. 2122160641Syongari * 2123160641Syongari * Note: We have to poke the IFS value before poking 2124160641Syongari * anything else. 2125160641Syongari */ 2126160641Syongari /* Tx/Rx MAC should be disabled before programming IFS.*/ 2127160641Syongari CSR_WRITE_4(sc, STGE_MACCtrl, MC_IFSSelect(MC_IFS96bit)); 2128160641Syongari 2129160641Syongari stge_vlan_setup(sc); 2130160641Syongari 2131160641Syongari if (sc->sc_rev >= 6) { /* >= B.2 */ 2132160641Syongari /* Multi-frag frame bug work-around. */ 2133160641Syongari CSR_WRITE_2(sc, STGE_DebugCtrl, 2134160641Syongari CSR_READ_2(sc, STGE_DebugCtrl) | 0x0200); 2135160641Syongari 2136160641Syongari /* Tx Poll Now bug work-around. */ 2137160641Syongari CSR_WRITE_2(sc, STGE_DebugCtrl, 2138160641Syongari CSR_READ_2(sc, STGE_DebugCtrl) | 0x0010); 2139160641Syongari /* Tx Poll Now bug work-around. */ 2140160641Syongari CSR_WRITE_2(sc, STGE_DebugCtrl, 2141160641Syongari CSR_READ_2(sc, STGE_DebugCtrl) | 0x0020); 2142160641Syongari } 2143160641Syongari 2144160641Syongari v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; 2145160641Syongari v |= MC_StatisticsEnable | MC_TxEnable | MC_RxEnable; 2146160641Syongari CSR_WRITE_4(sc, STGE_MACCtrl, v); 2147160641Syongari /* 2148160641Syongari * It seems that transmitting frames without checking the state of 2149160641Syongari * Rx/Tx MAC wedge the hardware. 2150160641Syongari */ 2151160641Syongari stge_start_tx(sc); 2152160641Syongari stge_start_rx(sc); 2153160641Syongari 2154169158Syongari sc->sc_link = 0; 2155160641Syongari /* 2156160641Syongari * Set the current media. 2157160641Syongari */ 2158160641Syongari mii_mediachg(mii); 2159160641Syongari 2160160641Syongari /* 2161160641Syongari * Start the one second MII clock. 2162160641Syongari */ 2163160641Syongari callout_reset(&sc->sc_tick_ch, hz, stge_tick, sc); 2164160641Syongari 2165160641Syongari /* 2166160641Syongari * ...all done! 2167160641Syongari */ 2168160641Syongari ifp->if_drv_flags |= IFF_DRV_RUNNING; 2169160641Syongari ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2170160641Syongari 2171160641Syongari out: 2172160641Syongari if (error != 0) 2173160641Syongari device_printf(sc->sc_dev, "interface not running\n"); 2174160641Syongari} 2175160641Syongari 2176160641Syongaristatic void 2177160641Syongaristge_vlan_setup(struct stge_softc *sc) 2178160641Syongari{ 2179160641Syongari struct ifnet *ifp; 2180160641Syongari uint32_t v; 2181160641Syongari 2182160641Syongari ifp = sc->sc_ifp; 2183160641Syongari /* 2184160641Syongari * The NIC always copy a VLAN tag regardless of STGE_MACCtrl 2185160641Syongari * MC_AutoVLANuntagging bit. 2186160641Syongari * MC_AutoVLANtagging bit selects which VLAN source to use 2187160641Syongari * between STGE_VLANTag and TFC. However TFC TFD_VLANTagInsert 2188160641Syongari * bit has priority over MC_AutoVLANtagging bit. So we always 2189160641Syongari * use TFC instead of STGE_VLANTag register. 2190160641Syongari */ 2191160641Syongari v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; 2192160641Syongari if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 2193160641Syongari v |= MC_AutoVLANuntagging; 2194160641Syongari else 2195160641Syongari v &= ~MC_AutoVLANuntagging; 2196160641Syongari CSR_WRITE_4(sc, STGE_MACCtrl, v); 2197160641Syongari} 2198160641Syongari 2199160641Syongari/* 2200160641Syongari * Stop transmission on the interface. 2201160641Syongari */ 2202160641Syongaristatic void 2203160641Syongaristge_stop(struct stge_softc *sc) 2204160641Syongari{ 2205160641Syongari struct ifnet *ifp; 2206160641Syongari struct stge_txdesc *txd; 2207160641Syongari struct stge_rxdesc *rxd; 2208160641Syongari uint32_t v; 2209160641Syongari int i; 2210160641Syongari 2211160641Syongari STGE_LOCK_ASSERT(sc); 2212160641Syongari /* 2213160641Syongari * Stop the one second clock. 2214160641Syongari */ 2215160641Syongari callout_stop(&sc->sc_tick_ch); 2216169157Syongari sc->sc_watchdog_timer = 0; 2217160641Syongari 2218160641Syongari /* 2219160641Syongari * Disable interrupts. 2220160641Syongari */ 2221160641Syongari CSR_WRITE_2(sc, STGE_IntEnable, 0); 2222160641Syongari 2223160641Syongari /* 2224160641Syongari * Stop receiver, transmitter, and stats update. 2225160641Syongari */ 2226160641Syongari stge_stop_rx(sc); 2227160641Syongari stge_stop_tx(sc); 2228160641Syongari v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; 2229160641Syongari v |= MC_StatisticsDisable; 2230160641Syongari CSR_WRITE_4(sc, STGE_MACCtrl, v); 2231160641Syongari 2232160641Syongari /* 2233160641Syongari * Stop the transmit and receive DMA. 2234160641Syongari */ 2235160641Syongari stge_dma_wait(sc); 2236160641Syongari CSR_WRITE_4(sc, STGE_TFDListPtrHi, 0); 2237160641Syongari CSR_WRITE_4(sc, STGE_TFDListPtrLo, 0); 2238160641Syongari CSR_WRITE_4(sc, STGE_RFDListPtrHi, 0); 2239160641Syongari CSR_WRITE_4(sc, STGE_RFDListPtrLo, 0); 2240160641Syongari 2241160641Syongari /* 2242160641Syongari * Free RX and TX mbufs still in the queues. 2243160641Syongari */ 2244160641Syongari for (i = 0; i < STGE_RX_RING_CNT; i++) { 2245160641Syongari rxd = &sc->sc_cdata.stge_rxdesc[i]; 2246160641Syongari if (rxd->rx_m != NULL) { 2247160641Syongari bus_dmamap_sync(sc->sc_cdata.stge_rx_tag, 2248160641Syongari rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 2249160641Syongari bus_dmamap_unload(sc->sc_cdata.stge_rx_tag, 2250160641Syongari rxd->rx_dmamap); 2251160641Syongari m_freem(rxd->rx_m); 2252160641Syongari rxd->rx_m = NULL; 2253160641Syongari } 2254160641Syongari } 2255160641Syongari for (i = 0; i < STGE_TX_RING_CNT; i++) { 2256160641Syongari txd = &sc->sc_cdata.stge_txdesc[i]; 2257160641Syongari if (txd->tx_m != NULL) { 2258160641Syongari bus_dmamap_sync(sc->sc_cdata.stge_tx_tag, 2259160641Syongari txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2260160641Syongari bus_dmamap_unload(sc->sc_cdata.stge_tx_tag, 2261160641Syongari txd->tx_dmamap); 2262160641Syongari m_freem(txd->tx_m); 2263160641Syongari txd->tx_m = NULL; 2264160641Syongari } 2265160641Syongari } 2266160641Syongari 2267160641Syongari /* 2268160641Syongari * Mark the interface down and cancel the watchdog timer. 2269160641Syongari */ 2270160641Syongari ifp = sc->sc_ifp; 2271160641Syongari ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2272169158Syongari sc->sc_link = 0; 2273160641Syongari} 2274160641Syongari 2275160641Syongaristatic void 2276160641Syongaristge_start_tx(struct stge_softc *sc) 2277160641Syongari{ 2278160641Syongari uint32_t v; 2279160641Syongari int i; 2280160641Syongari 2281160641Syongari v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; 2282160641Syongari if ((v & MC_TxEnabled) != 0) 2283160641Syongari return; 2284160641Syongari v |= MC_TxEnable; 2285160641Syongari CSR_WRITE_4(sc, STGE_MACCtrl, v); 2286160641Syongari CSR_WRITE_1(sc, STGE_TxDMAPollPeriod, 127); 2287160641Syongari for (i = STGE_TIMEOUT; i > 0; i--) { 2288160641Syongari DELAY(10); 2289160641Syongari v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; 2290160641Syongari if ((v & MC_TxEnabled) != 0) 2291160641Syongari break; 2292160641Syongari } 2293160641Syongari if (i == 0) 2294160641Syongari device_printf(sc->sc_dev, "Starting Tx MAC timed out\n"); 2295160641Syongari} 2296160641Syongari 2297160641Syongaristatic void 2298160641Syongaristge_start_rx(struct stge_softc *sc) 2299160641Syongari{ 2300160641Syongari uint32_t v; 2301160641Syongari int i; 2302160641Syongari 2303160641Syongari v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; 2304160641Syongari if ((v & MC_RxEnabled) != 0) 2305160641Syongari return; 2306160641Syongari v |= MC_RxEnable; 2307160641Syongari CSR_WRITE_4(sc, STGE_MACCtrl, v); 2308160641Syongari CSR_WRITE_1(sc, STGE_RxDMAPollPeriod, 1); 2309160641Syongari for (i = STGE_TIMEOUT; i > 0; i--) { 2310160641Syongari DELAY(10); 2311160641Syongari v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; 2312160641Syongari if ((v & MC_RxEnabled) != 0) 2313160641Syongari break; 2314160641Syongari } 2315160641Syongari if (i == 0) 2316160641Syongari device_printf(sc->sc_dev, "Starting Rx MAC timed out\n"); 2317160641Syongari} 2318160641Syongari 2319160641Syongaristatic void 2320160641Syongaristge_stop_tx(struct stge_softc *sc) 2321160641Syongari{ 2322160641Syongari uint32_t v; 2323160641Syongari int i; 2324160641Syongari 2325160641Syongari v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; 2326160641Syongari if ((v & MC_TxEnabled) == 0) 2327160641Syongari return; 2328160641Syongari v |= MC_TxDisable; 2329160641Syongari CSR_WRITE_4(sc, STGE_MACCtrl, v); 2330160641Syongari for (i = STGE_TIMEOUT; i > 0; i--) { 2331160641Syongari DELAY(10); 2332160641Syongari v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; 2333160641Syongari if ((v & MC_TxEnabled) == 0) 2334160641Syongari break; 2335160641Syongari } 2336160641Syongari if (i == 0) 2337160641Syongari device_printf(sc->sc_dev, "Stopping Tx MAC timed out\n"); 2338160641Syongari} 2339160641Syongari 2340160641Syongaristatic void 2341160641Syongaristge_stop_rx(struct stge_softc *sc) 2342160641Syongari{ 2343160641Syongari uint32_t v; 2344160641Syongari int i; 2345160641Syongari 2346160641Syongari v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; 2347160641Syongari if ((v & MC_RxEnabled) == 0) 2348160641Syongari return; 2349160641Syongari v |= MC_RxDisable; 2350160641Syongari CSR_WRITE_4(sc, STGE_MACCtrl, v); 2351160641Syongari for (i = STGE_TIMEOUT; i > 0; i--) { 2352160641Syongari DELAY(10); 2353160641Syongari v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; 2354160641Syongari if ((v & MC_RxEnabled) == 0) 2355160641Syongari break; 2356160641Syongari } 2357160641Syongari if (i == 0) 2358160641Syongari device_printf(sc->sc_dev, "Stopping Rx MAC timed out\n"); 2359160641Syongari} 2360160641Syongari 2361160641Syongaristatic void 2362160641Syongaristge_init_tx_ring(struct stge_softc *sc) 2363160641Syongari{ 2364160641Syongari struct stge_ring_data *rd; 2365160641Syongari struct stge_txdesc *txd; 2366160641Syongari bus_addr_t addr; 2367160641Syongari int i; 2368160641Syongari 2369160641Syongari STAILQ_INIT(&sc->sc_cdata.stge_txfreeq); 2370160641Syongari STAILQ_INIT(&sc->sc_cdata.stge_txbusyq); 2371160641Syongari 2372160641Syongari sc->sc_cdata.stge_tx_prod = 0; 2373160641Syongari sc->sc_cdata.stge_tx_cons = 0; 2374160641Syongari sc->sc_cdata.stge_tx_cnt = 0; 2375160641Syongari 2376160641Syongari rd = &sc->sc_rdata; 2377160641Syongari bzero(rd->stge_tx_ring, STGE_TX_RING_SZ); 2378160641Syongari for (i = 0; i < STGE_TX_RING_CNT; i++) { 2379160641Syongari if (i == (STGE_TX_RING_CNT - 1)) 2380160641Syongari addr = STGE_TX_RING_ADDR(sc, 0); 2381160641Syongari else 2382160641Syongari addr = STGE_TX_RING_ADDR(sc, i + 1); 2383160641Syongari rd->stge_tx_ring[i].tfd_next = htole64(addr); 2384160641Syongari rd->stge_tx_ring[i].tfd_control = htole64(TFD_TFDDone); 2385160641Syongari txd = &sc->sc_cdata.stge_txdesc[i]; 2386160641Syongari STAILQ_INSERT_TAIL(&sc->sc_cdata.stge_txfreeq, txd, tx_q); 2387160641Syongari } 2388160641Syongari 2389160641Syongari bus_dmamap_sync(sc->sc_cdata.stge_tx_ring_tag, 2390160641Syongari sc->sc_cdata.stge_tx_ring_map, 2391160641Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2392160641Syongari 2393160641Syongari} 2394160641Syongari 2395160641Syongaristatic int 2396160641Syongaristge_init_rx_ring(struct stge_softc *sc) 2397160641Syongari{ 2398160641Syongari struct stge_ring_data *rd; 2399160641Syongari bus_addr_t addr; 2400160641Syongari int i; 2401160641Syongari 2402160641Syongari sc->sc_cdata.stge_rx_cons = 0; 2403160641Syongari STGE_RXCHAIN_RESET(sc); 2404160641Syongari 2405160641Syongari rd = &sc->sc_rdata; 2406160641Syongari bzero(rd->stge_rx_ring, STGE_RX_RING_SZ); 2407160641Syongari for (i = 0; i < STGE_RX_RING_CNT; i++) { 2408160641Syongari if (stge_newbuf(sc, i) != 0) 2409160641Syongari return (ENOBUFS); 2410160641Syongari if (i == (STGE_RX_RING_CNT - 1)) 2411160641Syongari addr = STGE_RX_RING_ADDR(sc, 0); 2412160641Syongari else 2413160641Syongari addr = STGE_RX_RING_ADDR(sc, i + 1); 2414160641Syongari rd->stge_rx_ring[i].rfd_next = htole64(addr); 2415160641Syongari rd->stge_rx_ring[i].rfd_status = 0; 2416160641Syongari } 2417160641Syongari 2418160641Syongari bus_dmamap_sync(sc->sc_cdata.stge_rx_ring_tag, 2419160641Syongari sc->sc_cdata.stge_rx_ring_map, 2420160641Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2421160641Syongari 2422160641Syongari return (0); 2423160641Syongari} 2424160641Syongari 2425160641Syongari/* 2426160641Syongari * stge_newbuf: 2427160641Syongari * 2428160641Syongari * Add a receive buffer to the indicated descriptor. 2429160641Syongari */ 2430160641Syongaristatic int 2431160641Syongaristge_newbuf(struct stge_softc *sc, int idx) 2432160641Syongari{ 2433160641Syongari struct stge_rxdesc *rxd; 2434160641Syongari struct stge_rfd *rfd; 2435160641Syongari struct mbuf *m; 2436160641Syongari bus_dma_segment_t segs[1]; 2437160641Syongari bus_dmamap_t map; 2438160641Syongari int nsegs; 2439160641Syongari 2440243857Sglebius m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 2441160641Syongari if (m == NULL) 2442160641Syongari return (ENOBUFS); 2443160641Syongari m->m_len = m->m_pkthdr.len = MCLBYTES; 2444160641Syongari /* 2445160641Syongari * The hardware requires 4bytes aligned DMA address when JUMBO 2446160641Syongari * frame is used. 2447160641Syongari */ 2448160641Syongari if (sc->sc_if_framesize <= (MCLBYTES - ETHER_ALIGN)) 2449160641Syongari m_adj(m, ETHER_ALIGN); 2450160641Syongari 2451160641Syongari if (bus_dmamap_load_mbuf_sg(sc->sc_cdata.stge_rx_tag, 2452160641Syongari sc->sc_cdata.stge_rx_sparemap, m, segs, &nsegs, 0) != 0) { 2453160641Syongari m_freem(m); 2454160641Syongari return (ENOBUFS); 2455160641Syongari } 2456160641Syongari KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 2457160641Syongari 2458160641Syongari rxd = &sc->sc_cdata.stge_rxdesc[idx]; 2459160641Syongari if (rxd->rx_m != NULL) { 2460160641Syongari bus_dmamap_sync(sc->sc_cdata.stge_rx_tag, rxd->rx_dmamap, 2461160641Syongari BUS_DMASYNC_POSTREAD); 2462160641Syongari bus_dmamap_unload(sc->sc_cdata.stge_rx_tag, rxd->rx_dmamap); 2463160641Syongari } 2464160641Syongari map = rxd->rx_dmamap; 2465160641Syongari rxd->rx_dmamap = sc->sc_cdata.stge_rx_sparemap; 2466160641Syongari sc->sc_cdata.stge_rx_sparemap = map; 2467160641Syongari bus_dmamap_sync(sc->sc_cdata.stge_rx_tag, rxd->rx_dmamap, 2468160641Syongari BUS_DMASYNC_PREREAD); 2469160641Syongari rxd->rx_m = m; 2470160641Syongari 2471160641Syongari rfd = &sc->sc_rdata.stge_rx_ring[idx]; 2472160641Syongari rfd->rfd_frag.frag_word0 = 2473160641Syongari htole64(FRAG_ADDR(segs[0].ds_addr) | FRAG_LEN(segs[0].ds_len)); 2474160641Syongari rfd->rfd_status = 0; 2475160641Syongari 2476160641Syongari return (0); 2477160641Syongari} 2478160641Syongari 2479160641Syongari/* 2480160641Syongari * stge_set_filter: 2481160641Syongari * 2482160641Syongari * Set up the receive filter. 2483160641Syongari */ 2484160641Syongaristatic void 2485160641Syongaristge_set_filter(struct stge_softc *sc) 2486160641Syongari{ 2487160641Syongari struct ifnet *ifp; 2488160641Syongari uint16_t mode; 2489160641Syongari 2490160641Syongari STGE_LOCK_ASSERT(sc); 2491160641Syongari 2492160641Syongari ifp = sc->sc_ifp; 2493160641Syongari 2494160641Syongari mode = CSR_READ_2(sc, STGE_ReceiveMode); 2495160641Syongari mode |= RM_ReceiveUnicast; 2496160641Syongari if ((ifp->if_flags & IFF_BROADCAST) != 0) 2497160641Syongari mode |= RM_ReceiveBroadcast; 2498160641Syongari else 2499160641Syongari mode &= ~RM_ReceiveBroadcast; 2500160641Syongari if ((ifp->if_flags & IFF_PROMISC) != 0) 2501160641Syongari mode |= RM_ReceiveAllFrames; 2502160641Syongari else 2503160641Syongari mode &= ~RM_ReceiveAllFrames; 2504160641Syongari 2505160641Syongari CSR_WRITE_2(sc, STGE_ReceiveMode, mode); 2506160641Syongari} 2507160641Syongari 2508160641Syongaristatic void 2509160641Syongaristge_set_multi(struct stge_softc *sc) 2510160641Syongari{ 2511160641Syongari struct ifnet *ifp; 2512160641Syongari struct ifmultiaddr *ifma; 2513160641Syongari uint32_t crc; 2514160641Syongari uint32_t mchash[2]; 2515160641Syongari uint16_t mode; 2516160641Syongari int count; 2517160641Syongari 2518160641Syongari STGE_LOCK_ASSERT(sc); 2519160641Syongari 2520160641Syongari ifp = sc->sc_ifp; 2521160641Syongari 2522160641Syongari mode = CSR_READ_2(sc, STGE_ReceiveMode); 2523160641Syongari if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 2524160641Syongari if ((ifp->if_flags & IFF_PROMISC) != 0) 2525160641Syongari mode |= RM_ReceiveAllFrames; 2526160641Syongari else if ((ifp->if_flags & IFF_ALLMULTI) != 0) 2527160641Syongari mode |= RM_ReceiveMulticast; 2528160641Syongari CSR_WRITE_2(sc, STGE_ReceiveMode, mode); 2529160641Syongari return; 2530160641Syongari } 2531160641Syongari 2532160641Syongari /* clear existing filters. */ 2533160641Syongari CSR_WRITE_4(sc, STGE_HashTable0, 0); 2534160641Syongari CSR_WRITE_4(sc, STGE_HashTable1, 0); 2535160641Syongari 2536160641Syongari /* 2537160641Syongari * Set up the multicast address filter by passing all multicast 2538160641Syongari * addresses through a CRC generator, and then using the low-order 2539160641Syongari * 6 bits as an index into the 64 bit multicast hash table. The 2540160641Syongari * high order bits select the register, while the rest of the bits 2541160641Syongari * select the bit within the register. 2542160641Syongari */ 2543160641Syongari 2544160641Syongari bzero(mchash, sizeof(mchash)); 2545160641Syongari 2546160641Syongari count = 0; 2547195049Srwatson if_maddr_rlock(sc->sc_ifp); 2548160641Syongari TAILQ_FOREACH(ifma, &sc->sc_ifp->if_multiaddrs, ifma_link) { 2549160641Syongari if (ifma->ifma_addr->sa_family != AF_LINK) 2550160641Syongari continue; 2551160641Syongari crc = ether_crc32_be(LLADDR((struct sockaddr_dl *) 2552160641Syongari ifma->ifma_addr), ETHER_ADDR_LEN); 2553160641Syongari 2554160641Syongari /* Just want the 6 least significant bits. */ 2555160641Syongari crc &= 0x3f; 2556160641Syongari 2557160641Syongari /* Set the corresponding bit in the hash table. */ 2558160641Syongari mchash[crc >> 5] |= 1 << (crc & 0x1f); 2559160641Syongari count++; 2560160641Syongari } 2561195049Srwatson if_maddr_runlock(ifp); 2562160641Syongari 2563160641Syongari mode &= ~(RM_ReceiveMulticast | RM_ReceiveAllFrames); 2564160641Syongari if (count > 0) 2565160641Syongari mode |= RM_ReceiveMulticastHash; 2566160641Syongari else 2567160641Syongari mode &= ~RM_ReceiveMulticastHash; 2568160641Syongari 2569160641Syongari CSR_WRITE_4(sc, STGE_HashTable0, mchash[0]); 2570160641Syongari CSR_WRITE_4(sc, STGE_HashTable1, mchash[1]); 2571160641Syongari CSR_WRITE_2(sc, STGE_ReceiveMode, mode); 2572160641Syongari} 2573160641Syongari 2574160641Syongaristatic int 2575160641Syongarisysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 2576160641Syongari{ 2577160641Syongari int error, value; 2578160641Syongari 2579160641Syongari if (!arg1) 2580160641Syongari return (EINVAL); 2581160641Syongari value = *(int *)arg1; 2582160641Syongari error = sysctl_handle_int(oidp, &value, 0, req); 2583160641Syongari if (error || !req->newptr) 2584160641Syongari return (error); 2585160641Syongari if (value < low || value > high) 2586160641Syongari return (EINVAL); 2587160641Syongari *(int *)arg1 = value; 2588160641Syongari 2589160641Syongari return (0); 2590160641Syongari} 2591160641Syongari 2592160641Syongaristatic int 2593160641Syongarisysctl_hw_stge_rxint_nframe(SYSCTL_HANDLER_ARGS) 2594160641Syongari{ 2595160641Syongari return (sysctl_int_range(oidp, arg1, arg2, req, 2596160641Syongari STGE_RXINT_NFRAME_MIN, STGE_RXINT_NFRAME_MAX)); 2597160641Syongari} 2598160641Syongari 2599160641Syongaristatic int 2600160641Syongarisysctl_hw_stge_rxint_dmawait(SYSCTL_HANDLER_ARGS) 2601160641Syongari{ 2602160641Syongari return (sysctl_int_range(oidp, arg1, arg2, req, 2603160641Syongari STGE_RXINT_DMAWAIT_MIN, STGE_RXINT_DMAWAIT_MAX)); 2604160641Syongari} 2605