Searched refs:timing_cfg_3 (Results 1 - 21 of 21) sorted by relevance
| /u-boot/drivers/ddr/fsl/ |
| H A D | mpc85xx_ddr_gen2.c | 67 out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3);
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| H A D | arm_ddr_gen3.c | 93 ddr_out32(&ddr->timing_cfg_3, regs->timing_cfg_3);
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| H A D | util.c | 248 cas_lat += ((ddr_in32(&ddr->timing_cfg_3) >> 12) & 3) << 4;
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| H A D | fsl_ddr_gen4.c | 169 ddr_out32(&ddr->timing_cfg_3, regs->timing_cfg_3);
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| H A D | mpc85xx_ddr_gen3.c | 125 out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3);
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| H A D | ctrl_regs.c | 493 ddr->timing_cfg_3 = (0
503 debug("FSLDDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3);
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| H A D | interactive.c | 632 CFG_REGS(timing_cfg_3),
723 CFG_REGS(timing_cfg_3),
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| /u-boot/board/freescale/ls1043ardb/ |
| H A D | ddr.h | 59 .timing_cfg_3 = 0x010C1000,
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| /u-boot/board/gdsys/mpc8308/ |
| H A D | sdram.c | 52 out_be32(&im->ddr.timing_cfg_3, CFG_SYS_DDR_TIMING_3);
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| /u-boot/board/kontron/sl28/ |
| H A D | ddr.c | 28 .timing_cfg_3 = 0x010c1000,
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| /u-boot/board/freescale/ls1021atsn/ |
| H A D | ls1021atsn.c | 42 out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3);
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| /u-boot/board/freescale/ls1021aiot/ |
| H A D | ls1021aiot.c | 66 out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3);
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| /u-boot/board/freescale/mpc837xerdb/ |
| H A D | mpc837xerdb.c | 119 im->ddr.timing_cfg_3 = CFG_SYS_DDR_TIMING_3;
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| /u-boot/board/freescale/p1_p2_rdb_pc/ |
| H A D | ddr.c | 220 .timing_cfg_3 = CFG_SYS_DDR_TIMING_3,
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| /u-boot/board/keymile/km83xx/ |
| H A D | km83xx.c | 221 out_be32(&im->ddr.timing_cfg_3, CFG_SYS_DDR_TIMING_3);
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| /u-boot/include/ |
| H A D | fsl_immap.h | 33 u32 timing_cfg_3; /* SDRAM Timing Configuration 3 */ member in struct:ccsr_ddr
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| H A D | fsl_ddr_sdram.h | 248 unsigned int timing_cfg_3; member in struct:fsl_ddr_cfg_regs_s
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| /u-boot/board/cssi/cmpcpro/ |
| H A D | cmpcpro.c | 311 out_be32(&im->ddr.timing_cfg_3, CFG_SYS_DDR_TIMING_3);
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| /u-boot/board/freescale/ls1021atwr/ |
| H A D | ls1021atwr.c | 157 out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3);
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| /u-boot/arch/powerpc/include/asm/ |
| H A D | immap_83xx.h | 287 u32 timing_cfg_3; /* SDRAM Timing Configuration 3 */ member in struct:ddr83xx
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| /u-boot/drivers/ram/ |
| H A D | mpc83xx_sdram.c | 524 out_be32(&im->ddr.timing_cfg_3, ext_refresh_rec_mask);
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