Searched refs:sdram_cfg (Results 1 - 20 of 20) sorted by relevance

/u-boot/drivers/ddr/fsl/
H A Dutil.c192 uint32_t sdram_cfg = ddr_in32(&ddr->sdram_cfg); local
196 if ((!(sdram_cfg & SDRAM_CFG_MEM_EN)) ||
199 sdram_cfg = ddr_in32(&ddr->sdram_cfg);
203 if ((!(sdram_cfg & SDRAM_CFG_MEM_EN)) ||
206 sdram_cfg = ddr_in32(&ddr->sdram_cfg);
210 if (!(sdram_cfg & SDRAM_CFG_MEM_EN)) {
216 switch ((sdram_cfg
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H A Darm_ddr_gen3.c174 ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg);
194 temp_sdram_cfg = (ddr_in32(&ddr->sdram_cfg) | SDRAM_CFG_BI);
197 temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI;
199 ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN);
224 bus_width = 3 - ((ddr_in32(&ddr->sdram_cfg) & SDRAM_CFG_DBW_MASK)
H A Dmpc85xx_ddr_gen3.c210 out_be32(&ddr->sdram_cfg, temp_sdram_cfg);
225 out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_BI | SDRAM_CFG_MEM_EN);
338 out_be32(&ddr->sdram_cfg, temp_sdram_cfg);
400 if ((((in_be32(&ddr->sdram_cfg) >> 24) & 0x7) == SDRAM_TYPE_DDR2)
401 && in_be32(&ddr->sdram_cfg) & 0x80000) {
443 temp_sdram_cfg = (in_be32(&ddr->sdram_cfg) | SDRAM_CFG_BI);
446 temp_sdram_cfg = (in_be32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI);
449 out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN);
474 bus_width = 3 - ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK)
581 setbits_be32(&ddr->sdram_cfg,
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H A Dmpc85xx_ddr_gen1.c59 out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg);
H A Dmpc85xx_ddr_gen2.c88 out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg);
H A Dfsl_ddr_gen4.c330 ddr_out32(&ddr->sdram_cfg, temp32);
351 temp32 = (ddr_in32(&ddr->sdram_cfg) | SDRAM_CFG_BI);
354 temp32 = ddr_in32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI;
356 ddr_out32(&ddr->sdram_cfg, temp32 | SDRAM_CFG_MEM_EN);
514 bus_width = 3 - ((ddr_in32(&ddr->sdram_cfg) & SDRAM_CFG_DBW_MASK)
H A Dctrl_regs.c2584 u32 sdram_cfg, i, tmp, lanes, ddr_type; local
2587 sdram_cfg = ddr_in32(&ddr->sdram_cfg);
2588 if (sdram_cfg & SDRAM_CFG_32_BE)
2590 else if (sdram_cfg & SDRAM_CFG_16_BE)
2595 if (sdram_cfg & SDRAM_CFG_ECC_EN)
2626 ddr_type = (sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) >>
/u-boot/board/socrates/
H A Dsdram.c35 ddr->sdram_cfg = 0;
50 ddr->sdram_cfg = CFG_SYS_DDR_CONFIG;
/u-boot/board/gdsys/mpc8308/
H A Dsdram.c57 out_be32(&im->ddr.sdram_cfg, CFG_SYS_DDR_SDRAM_CFG);
66 setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
/u-boot/arch/powerpc/cpu/mpc83xx/
H A Dspd_sdram.c38 printf(" (DDR%d", ((ddr->sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK)
42 if ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) == SDRAM_CFG_DBW_16)
44 else if ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) == SDRAM_CFG_DBW_32)
49 if (ddr->sdram_cfg & SDRAM_CFG_32_BE)
55 if (ddr->sdram_cfg & SDRAM_CFG_ECC_EN)
157 unsigned int sdram_cfg; local
165 clrsetbits_be32(&ddr->sdram_cfg, SDRAM_CFG_MEM_EN, 0);
781 * Figure out the settings for the sdram_cfg register. Build up
782 * the value in 'sdram_cfg' before writing since the write into
786 * sdram_cfg[
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H A Decc.c24 (ddr->sdram_cfg & SDRAM_CFG_ECC_EN) ? "ON" : "OFF");
/u-boot/board/freescale/ls1021atsn/
H A Dls1021atsn.c34 out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG);
98 out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | temp_sdram_cfg);
/u-boot/board/freescale/ls1021aiot/
H A Dls1021aiot.c58 out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG);
98 out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | temp_sdram_cfg);
/u-boot/board/freescale/mpc837xerdb/
H A Dmpc837xerdb.c120 im->ddr.sdram_cfg = CFG_SYS_DDR_SDRAM_CFG;
128 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
/u-boot/board/keymile/km83xx/
H A Dkm83xx.c222 out_be32(&im->ddr.sdram_cfg, CFG_SYS_DDR_SDRAM_CFG);
229 setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
/u-boot/drivers/ram/
H A Dmpc83xx_sdram.c343 u32 sdram_cfg; local
920 sdram_cfg = self_refresh << SDRAM_CFG_SREN_SHIFT |
933 out_be32(&im->ddr.sdram_cfg, sdram_cfg);
1051 setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
/u-boot/board/cssi/cmpcpro/
H A Dcmpcpro.c312 out_be32(&im->ddr.sdram_cfg, CFG_SYS_DDR_SDRAM_CFG);
319 setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
/u-boot/include/
H A Dfsl_immap.h37 u32 sdram_cfg; /* SDRAM Control Configuration */ member in struct:ccsr_ddr
/u-boot/board/freescale/ls1021atwr/
H A Dls1021atwr.c149 out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG);
213 out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | temp_sdram_cfg);
/u-boot/arch/powerpc/include/asm/
H A Dimmap_83xx.h291 u32 sdram_cfg; /* SDRAM Control Configuration */ member in struct:ddr83xx

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