Lines Matching refs:sdram_cfg
38 printf(" (DDR%d", ((ddr->sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK)
42 if ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) == SDRAM_CFG_DBW_16)
44 else if ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) == SDRAM_CFG_DBW_32)
49 if (ddr->sdram_cfg & SDRAM_CFG_32_BE)
55 if (ddr->sdram_cfg & SDRAM_CFG_ECC_EN)
157 unsigned int sdram_cfg;
165 clrsetbits_be32(&ddr->sdram_cfg, SDRAM_CFG_MEM_EN, 0);
781 * Figure out the settings for the sdram_cfg register. Build up
782 * the value in 'sdram_cfg' before writing since the write into
786 * sdram_cfg[0] = 1 (ddr sdram logic enable)
787 * sdram_cfg[1] = 1 (self-refresh-enable)
788 * sdram_cfg[5:7] = (SDRAM type = DDR SDRAM)
791 * sdram_cfg[12] = 0 (32_BE =0 , 64 bit bus mode)
792 * sdram_cfg[13] = 0 (8_BE =0, 4-beat bursts)
799 sdram_cfg = (0
805 /* sdram_cfg[3] = RD_EN - registered DIMM enable */
807 sdram_cfg |= SDRAM_CFG_RD_EN;
812 sdram_cfg |= SDRAM_CFG_32_BE | SDRAM_CFG_8_BE;
814 sdram_cfg |= SDRAM_CFG_32_BE;
820 /* Enable ECC with sdram_cfg[2] */
822 sdram_cfg |= 0x20000000;
838 ddr->sdram_cfg = sdram_cfg;
843 debug("DDR:sdram_cfg=0x%08x\n", ddr->sdram_cfg);