| /u-boot/drivers/ddr/marvell/a38x/ |
| H A D | mv_ddr4_training.h | 30 u16 mv_ddr4_rtt_wr_to_odt(u16 rtt_wr);
|
| H A D | mv_ddr_topology.c | 338 unsigned int rtt_wr = MV_DDR_RTT_WR_RZQ_LAST; local
341 rtt_wr = tm->edata.mem_edata.rtt_wr[cs_num - 1];
343 if (rtt_wr >= MV_DDR_RTT_WR_RZQ_LAST) {
344 printf("error: %s: unsupported rtt_wr parameter found\n", __func__);
345 rtt_wr = PARAM_UNDEFINED;
348 return rtt_wr;
|
| H A D | ddr_topology_def.h | 78 enum mv_ddr_rtt_wr_evalue rtt_wr[MAX_CS_NUM]; member in struct:mv_ddr_mem_edata
|
| H A D | mv_ddr4_training.c | 132 u16 mv_ddr4_rtt_wr_to_odt(u16 rtt_wr) argument
136 if (rtt_wr == 0)
138 else if (rtt_wr == (1 << 9))
140 else if (rtt_wr == (2 << 9))
145 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO, ("mv_ddr4_rtt_wr_to_odt rtt_wr = %d, odt = %d\n", rtt_wr, odt));
|
| /u-boot/board/engicam/common/ |
| H A D | spl.c | 231 .rtt_wr = 2,
263 .rtt_wr = 1,
280 .rtt_wr = 1,
327 .rtt_wr = 2,
|
| /u-boot/board/udoo/ |
| H A D | udoo_spl.c | 191 .rtt_wr = 2,
220 mem_qdl.rtt_wr = 1;
227 mem_qdl.rtt_wr = 2;
|
| /u-boot/board/bsh/imx6ulz_smm_m2/ |
| H A D | spl.c | 76 .rtt_wr = 0,
|
| /u-boot/board/compulab/cm_fx6/ |
| H A D | spl.c | 105 .rtt_wr = 0,
172 .rtt_wr = 0,
|
| /u-boot/drivers/ddr/fsl/ |
| H A D | ctrl_regs.c | 986 unsigned int rtt_wr = 0; /* Rtt_WR - dynamic ODT off */ local
994 rtt_wr = popts->rtt_wr_override_value;
996 rtt_wr = popts->cs_local_opts[0].odt_rtt_wr;
1003 | ((rtt_wr & 0x3) << 9)
1027 rtt_wr = popts->rtt_wr_override_value;
1029 rtt_wr = popts->cs_local_opts[i].odt_rtt_wr;
1032 esdmode2 |= (rtt_wr & 0x3) << 9;
1073 unsigned int rtt_wr = 0; /* Rtt_WR - dynamic ODT off */ local
1080 rtt_wr = popts->rtt_wr_override_value;
1082 rtt_wr
[all...] |
| /u-boot/board/liebherr/mccmon6/ |
| H A D | spl.c | 185 .rtt_wr = 0,
226 .rtt_wr = 0,
243 .rtt_wr = 0,
|
| /u-boot/board/wandboard/ |
| H A D | spl.c | 233 .rtt_wr = 0,
276 .rtt_wr = 0,
295 .rtt_wr = 0,
|
| /u-boot/arch/arm/mach-imx/mx6/ |
| H A D | litesom.c | 124 .rtt_wr = 2,
|
| H A D | opos6ul.c | 124 .rtt_wr = 2,
|
| /u-boot/board/seeed/npi_imx6ull/ |
| H A D | spl.c | 57 .rtt_wr = 1,
|
| /u-boot/board/phytec/pcl063/ |
| H A D | spl.c | 59 .rtt_wr = 1,
|
| /u-boot/board/technexion/pico-imx6ul/ |
| H A D | spl.c | 76 .rtt_wr = 0,
|
| /u-boot/board/myir/mys_6ulx/ |
| H A D | spl.c | 57 .rtt_wr = 1,
|
| /u-boot/board/bticino/mamoj/ |
| H A D | spl.c | 124 .rtt_wr = 1,
|
| /u-boot/board/variscite/dart_6ul/ |
| H A D | spl.c | 69 .rtt_wr = 2,
|
| /u-boot/board/freescale/mx6ul_14x14_evk/ |
| H A D | mx6ul_14x14_evk.c | 416 .rtt_wr = 0, /* LPDDR2 does not need rtt_wr rtt_nom */
452 .rtt_wr = 2,
|
| /u-boot/board/kontron/sl-mx6ul/ |
| H A D | spl.c | 243 .rtt_wr = 2,
|
| /u-boot/board/liebherr/display5/ |
| H A D | spl.c | 255 .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */
|
| /u-boot/board/phytec/pcm058/ |
| H A D | pcm058.c | 214 .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */
|
| /u-boot/board/technexion/pico-imx6/ |
| H A D | spl.c | 193 .rtt_wr = 0,
|
| /u-boot/board/k+p/kp_imx6q_tpc/ |
| H A D | kp_imx6q_tpc_spl.c | 169 .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */
|