1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2018 Collabora Ltd.
4 *
5 * Based on board/ccv/xpress/spl.c:
6 * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
7 */
8
9#include <common.h>
10#include <init.h>
11#include <spl.h>
12#include <asm/arch/clock.h>
13#include <asm/io.h>
14#include <asm/arch/mx6-ddr.h>
15#include <asm/arch/mx6-pins.h>
16#include <asm/arch/crm_regs.h>
17#include <asm/arch/sys_proto.h>
18#include <fsl_esdhc_imx.h>
19
20/* Configuration for Micron MT41K256M16TW-107 IT:P, 32M x 16 x 8 -> 256MiB */
21
22static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
23	.grp_addds = 0x00000030,
24	.grp_ddrmode_ctl = 0x00020000,
25	.grp_b0ds = 0x00000030,
26	.grp_ctlds = 0x00000030,
27	.grp_b1ds = 0x00000030,
28	.grp_ddrpke = 0x00000000,
29	.grp_ddrmode = 0x00020000,
30	.grp_ddr_type = 0x000c0000,
31};
32
33static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
34	.dram_dqm0 = 0x00000030,
35	.dram_dqm1 = 0x00000030,
36	.dram_ras = 0x00000030,
37	.dram_cas = 0x00000030,
38	.dram_odt0 = 0x00000030,
39	.dram_odt1 = 0x00000030,
40	.dram_sdba2 = 0x00000000,
41	.dram_sdclk_0 = 0x00000030,
42	.dram_sdqs0 = 0x00000030,
43	.dram_sdqs1 = 0x00000030,
44	.dram_reset = 0x00000030,
45};
46
47static struct mx6_mmdc_calibration mx6_mmcd_calib = {
48	.p0_mpwldectrl0 = 0x00000000,
49	.p0_mpdgctrl0 = 0x41480148,
50	.p0_mprddlctl = 0x40403E42,
51	.p0_mpwrdlctl = 0x40405852,
52};
53
54struct mx6_ddr_sysinfo ddr_sysinfo = {
55	.dsize = 0,		/* Bus size = 16bit */
56	.cs_density = 18,
57	.ncs = 1,
58	.cs1_mirror = 0,
59	.rtt_wr = 1,
60	.rtt_nom = 1,
61	.walat = 1,		/* Write additional latency */
62	.ralat = 5,		/* Read additional latency */
63	.mif3_mode = 3,		/* Command prediction working mode */
64	.bi_on = 1,		/* Bank interleaving enabled */
65	.pd_fast_exit = 1,
66	.sde_to_rst = 0x10,	/* 14 cycles, 200us (JEDEC default) */
67	.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
68	.ddr_type = DDR_TYPE_DDR3,
69	.refsel = 1,		/* Refresh cycles at 32KHz */
70	.refr = 7,		/* 8 refresh commands per refresh cycle */
71};
72
73static struct mx6_ddr3_cfg mem_ddr = {
74	.mem_speed = 933,
75	.density = 4,
76	.width = 16,
77	.banks = 8,
78	.rowaddr = 14,
79	.coladdr = 10,
80	.pagesz = 1,
81	.trcd = 1391,
82	.trcmin = 4791,
83	.trasmin = 3400,
84};
85
86static void ccgr_init(void)
87{
88	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
89
90	writel(0xFFFFFFFF, &ccm->CCGR0);
91	writel(0xFFFFFFFF, &ccm->CCGR1);
92	writel(0xFFFFFFFF, &ccm->CCGR2);
93	writel(0xFFFFFFFF, &ccm->CCGR3);
94	writel(0xFFFFFFFF, &ccm->CCGR4);
95	writel(0xFFFFFFFF, &ccm->CCGR5);
96	writel(0xFFFFFFFF, &ccm->CCGR6);
97}
98
99static void spl_dram_init(void)
100{
101	mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
102	mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
103}
104
105#ifdef CONFIG_FSL_ESDHC_IMX
106
107#define USDHC_PAD_CTRL (PAD_CTL_PKE         | PAD_CTL_PUE       | \
108			PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW | \
109			PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | \
110			PAD_CTL_HYS)
111
112static iomux_v3_cfg_t const usdhc1_pads[] = {
113	MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
114	MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
115	MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
116	MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
117	MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
118	MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
119	MX6_PAD_UART1_RTS_B__USDHC1_CD_B | MUX_PAD_CTRL(USDHC_PAD_CTRL),
120};
121
122#ifndef CONFIG_NAND_MXS
123static iomux_v3_cfg_t const usdhc2_pads[] = {
124	MX6_PAD_NAND_RE_B__USDHC2_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
125	MX6_PAD_NAND_WE_B__USDHC2_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
126	MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
127	MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
128	MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
129	MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
130	MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
131	MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
132	MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
133	MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
134};
135#endif
136
137static struct fsl_esdhc_cfg usdhc_cfg[] = {
138	{
139		.esdhc_base = USDHC1_BASE_ADDR,
140		.max_bus_width = 4,
141	},
142#ifndef CONFIG_NAND_MXS
143	{
144		.esdhc_base = USDHC2_BASE_ADDR,
145		.max_bus_width = 8,
146	},
147#endif
148};
149
150int board_mmc_getcd(struct mmc *mmc)
151{
152	return 1;
153}
154
155int board_mmc_init(struct bd_info *bis)
156{
157	int i, ret;
158
159	for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) {
160		switch (i) {
161		case 0:
162			SETUP_IOMUX_PADS(usdhc1_pads);
163			usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
164			break;
165#ifndef CONFIG_NAND_MXS
166		case 1:
167			SETUP_IOMUX_PADS(usdhc2_pads);
168			usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
169			break;
170#endif
171		default:
172			printf("Warning - USDHC%d controller not supporting\n",
173			       i + 1);
174			return 0;
175		}
176
177		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
178		if (ret) {
179			printf("Warning: failed to initialize mmc dev %d\n", i);
180			return ret;
181		}
182	}
183
184	return 0;
185}
186
187#endif /* CONFIG_FSL_ESDHC_IMX */
188
189void board_init_f(ulong dummy)
190{
191	ccgr_init();
192
193	/* Setup AIPS and disable watchdog */
194	arch_cpu_init();
195
196	/* Setup iomux and fec */
197	board_early_init_f();
198
199	/* Setup GP timer */
200	timer_init();
201
202	/* UART clocks enabled and gd valid - init serial console */
203	preloader_console_init();
204
205	/* DDR initialization */
206	spl_dram_init();
207}
208