1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (C) 2017 DENX Software Engineering 4 * Lukasz Majewski, DENX Software Engineering, lukma@denx.de 5 */ 6 7#include <common.h> 8#include <cpu_func.h> 9#include <env.h> 10#include <image.h> 11#include <init.h> 12#include <log.h> 13#include <serial.h> 14#include <spl.h> 15#include <asm/global_data.h> 16#include <linux/delay.h> 17#include <linux/libfdt.h> 18#include <asm/io.h> 19#include <asm/arch/clock.h> 20#include <asm/arch/mx6-ddr.h> 21#include <asm/arch/mx6-pins.h> 22#include "asm/arch/crm_regs.h" 23#include <asm/arch/sys_proto.h> 24#include <asm/arch/imx-regs.h> 25#include "asm/arch/iomux.h" 26#include <asm/mach-imx/iomux-v3.h> 27#include <asm/gpio.h> 28#include <asm/sections.h> 29#include <fsl_esdhc_imx.h> 30#include <netdev.h> 31#include <bootcount.h> 32#include <watchdog.h> 33#include "common.h" 34 35DECLARE_GLOBAL_DATA_PTR; 36 37static const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = { 38 .dram_sdclk_0 = 0x00000030, 39 .dram_sdclk_1 = 0x00000030, 40 .dram_cas = 0x00000030, 41 .dram_ras = 0x00000030, 42 .dram_reset = 0x00000030, 43 .dram_sdcke0 = 0x00003000, 44 .dram_sdcke1 = 0x00003000, 45 .dram_sdba2 = 0x00000000, 46 .dram_sdodt0 = 0x00000030, 47 .dram_sdodt1 = 0x00000030, 48 49 .dram_sdqs0 = 0x00000030, 50 .dram_sdqs1 = 0x00000030, 51 .dram_sdqs2 = 0x00000030, 52 .dram_sdqs3 = 0x00000030, 53 .dram_sdqs4 = 0x00000030, 54 .dram_sdqs5 = 0x00000030, 55 .dram_sdqs6 = 0x00000030, 56 .dram_sdqs7 = 0x00000030, 57 58 .dram_dqm0 = 0x00000030, 59 .dram_dqm1 = 0x00000030, 60 .dram_dqm2 = 0x00000030, 61 .dram_dqm3 = 0x00000030, 62 .dram_dqm4 = 0x00000030, 63 .dram_dqm5 = 0x00000030, 64 .dram_dqm6 = 0x00000030, 65 .dram_dqm7 = 0x00000030, 66}; 67 68static const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = { 69 .grp_ddr_type = 0x000c0000, 70 .grp_ddrmode_ctl = 0x00020000, 71 .grp_ddrpke = 0x00000000, 72 .grp_addds = 0x00000030, 73 .grp_ctlds = 0x00000030, 74 .grp_ddrmode = 0x00020000, 75 .grp_b0ds = 0x00000030, 76 .grp_b1ds = 0x00000030, 77 .grp_b2ds = 0x00000030, 78 .grp_b3ds = 0x00000030, 79 .grp_b4ds = 0x00000030, 80 .grp_b5ds = 0x00000030, 81 .grp_b6ds = 0x00000030, 82 .grp_b7ds = 0x00000030, 83}; 84 85/* 4x128Mx16.cfg */ 86static const struct mx6_mmdc_calibration mx6_4x256mx16_mmdc_calib = { 87 .p0_mpwldectrl0 = 0x002D0028, 88 .p0_mpwldectrl1 = 0x0032002D, 89 .p1_mpwldectrl0 = 0x00210036, 90 .p1_mpwldectrl1 = 0x0019002E, 91 .p0_mpdgctrl0 = 0x4349035C, 92 .p0_mpdgctrl1 = 0x0348033D, 93 .p1_mpdgctrl0 = 0x43550362, 94 .p1_mpdgctrl1 = 0x03520316, 95 .p0_mprddlctl = 0x41393940, 96 .p1_mprddlctl = 0x3F3A3C47, 97 .p0_mpwrdlctl = 0x413A423A, 98 .p1_mpwrdlctl = 0x4042483E, 99}; 100 101/* MT41K128M16JT-125 (2Gb density) */ 102static const struct mx6_ddr3_cfg mt41k128m16jt_125 = { 103 .mem_speed = 1600, 104 .density = 2, 105 .width = 16, 106 .banks = 8, 107 .rowaddr = 14, 108 .coladdr = 10, 109 .pagesz = 2, 110 .trcd = 1375, 111 .trcmin = 4875, 112 .trasmin = 3500, 113}; 114 115iomux_v3_cfg_t const uart_console_pads[] = { 116 /* UART5 */ 117 MX6_PAD_CSI0_DAT14__UART5_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 118 MX6_PAD_CSI0_DAT15__UART5_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 119 MX6_PAD_CSI0_DAT18__UART5_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), 120 MX6_PAD_CSI0_DAT19__UART5_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), 121}; 122 123void displ5_set_iomux_uart_spl(void) 124{ 125 SETUP_IOMUX_PADS(uart_console_pads); 126} 127 128iomux_v3_cfg_t const misc_pads_spl[] = { 129 /* Emergency recovery pin */ 130 MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), 131}; 132 133void displ5_set_iomux_misc_spl(void) 134{ 135 SETUP_IOMUX_PADS(misc_pads_spl); 136} 137 138#ifdef CONFIG_MXC_SPI 139iomux_v3_cfg_t const ecspi2_pads[] = { 140 /* SPI2, NOR Flash nWP, CS0 */ 141 MX6_PAD_CSI0_DAT10__ECSPI2_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), 142 MX6_PAD_CSI0_DAT9__ECSPI2_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), 143 MX6_PAD_CSI0_DAT8__ECSPI2_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), 144 MX6_PAD_CSI0_DAT11__GPIO5_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), 145 MX6_PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), 146}; 147 148int board_spi_cs_gpio(unsigned int bus, unsigned int cs) 149{ 150 if (bus != 1 || cs != 0) 151 return -EINVAL; 152 153 return IMX_GPIO_NR(5, 29); 154} 155 156void displ5_set_iomux_ecspi_spl(void) 157{ 158 SETUP_IOMUX_PADS(ecspi2_pads); 159} 160 161#else 162void displ5_set_iomux_ecspi_spl(void) {} 163#endif 164 165#ifdef CONFIG_FSL_ESDHC_IMX 166iomux_v3_cfg_t const usdhc4_pads[] = { 167 MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 168 MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 169 MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 170 MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 171 MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 172 MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 173 MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 174 MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 175 MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 176 MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 177 MX6_PAD_NANDF_ALE__SD4_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL), 178}; 179 180void displ5_set_iomux_usdhc_spl(void) 181{ 182 SETUP_IOMUX_PADS(usdhc4_pads); 183} 184 185#else 186void displ5_set_iomux_usdhc_spl(void) {} 187#endif 188 189static void ccgr_init(void) 190{ 191 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 192 193 writel(0x00C03F3F, &ccm->CCGR0); 194 writel(0x0030FC3F, &ccm->CCGR1); 195 writel(0x0FFFCFC0, &ccm->CCGR2); 196 writel(0x3FF00000, &ccm->CCGR3); 197 writel(0x00FFF300, &ccm->CCGR4); 198 writel(0x0F0000C3, &ccm->CCGR5); 199 writel(0x000003FF, &ccm->CCGR6); 200} 201 202#ifdef CONFIG_MX6_DDRCAL 203static void spl_dram_print_cal(struct mx6_ddr_sysinfo const *sysinfo) 204{ 205 struct mx6_mmdc_calibration calibration = {0}; 206 207 mmdc_read_calibration(sysinfo, &calibration); 208 209 debug(".p0_mpdgctrl0\t= 0x%08X\n", calibration.p0_mpdgctrl0); 210 debug(".p0_mpdgctrl1\t= 0x%08X\n", calibration.p0_mpdgctrl1); 211 debug(".p0_mprddlctl\t= 0x%08X\n", calibration.p0_mprddlctl); 212 debug(".p0_mpwrdlctl\t= 0x%08X\n", calibration.p0_mpwrdlctl); 213 debug(".p0_mpwldectrl0\t= 0x%08X\n", calibration.p0_mpwldectrl0); 214 debug(".p0_mpwldectrl1\t= 0x%08X\n", calibration.p0_mpwldectrl1); 215 debug(".p1_mpdgctrl0\t= 0x%08X\n", calibration.p1_mpdgctrl0); 216 debug(".p1_mpdgctrl1\t= 0x%08X\n", calibration.p1_mpdgctrl1); 217 debug(".p1_mprddlctl\t= 0x%08X\n", calibration.p1_mprddlctl); 218 debug(".p1_mpwrdlctl\t= 0x%08X\n", calibration.p1_mpwrdlctl); 219 debug(".p1_mpwldectrl0\t= 0x%08X\n", calibration.p1_mpwldectrl0); 220 debug(".p1_mpwldectrl1\t= 0x%08X\n", calibration.p1_mpwldectrl1); 221} 222 223static void spl_dram_perform_cal(struct mx6_ddr_sysinfo const *sysinfo) 224{ 225 int ret; 226 227 /* Perform DDR DRAM calibration */ 228 udelay(100); 229 ret = mmdc_do_write_level_calibration(sysinfo); 230 if (ret) { 231 printf("DDR: Write level calibration error [%d]\n", ret); 232 return; 233 } 234 235 ret = mmdc_do_dqs_calibration(sysinfo); 236 if (ret) { 237 printf("DDR: DQS calibration error [%d]\n", ret); 238 return; 239 } 240 241 spl_dram_print_cal(sysinfo); 242} 243#endif /* CONFIG_MX6_DDRCAL */ 244 245static void spl_dram_init(void) 246{ 247 struct mx6_ddr_sysinfo sysinfo = { 248 /* width of data bus:0=16,1=32,2=64 */ 249 .dsize = 2, 250 /* config for full 4GB range so that get_mem_size() works */ 251 .cs_density = 32, /* 32Gb per CS */ 252 /* single chip select */ 253 .ncs = 1, 254 .cs1_mirror = 0, 255 .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */ 256 .rtt_nom = 2 /*DDR3_RTT_120_OHM*/, /* RTT_Nom = RZQ/2 */ 257 .walat = 1, /* Write additional latency */ 258 .ralat = 5, /* Read additional latency */ 259 .mif3_mode = 3, /* Command prediction working mode */ 260 .bi_on = 1, /* Bank interleaving enabled */ 261 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ 262 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ 263 .pd_fast_exit = 1, /* enable precharge power-down fast exit */ 264 .ddr_type = DDR_TYPE_DDR3, 265 .refsel = 1, /* Refresh cycles at 32KHz */ 266 .refr = 7, /* 8 refresh commands per refresh cycle */ 267 }; 268 269 mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs); 270 mx6_dram_cfg(&sysinfo, &mx6_4x256mx16_mmdc_calib, &mt41k128m16jt_125); 271 272#ifdef CONFIG_MX6_DDRCAL 273 spl_dram_perform_cal(&sysinfo); 274#endif 275} 276 277#ifdef CONFIG_SPL_SPI 278static void displ5_init_ecspi(void) 279{ 280 displ5_set_iomux_ecspi_spl(); 281 enable_spi_clk(1, 1); 282} 283#else 284static inline void displ5_init_ecspi(void) { } 285#endif 286 287#ifdef CONFIG_SPL_MMC 288static struct fsl_esdhc_cfg usdhc_cfg = { 289 .esdhc_base = USDHC4_BASE_ADDR, 290 .max_bus_width = 8, 291}; 292 293int board_mmc_init(struct bd_info *bd) 294{ 295 displ5_set_iomux_usdhc_spl(); 296 297 usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); 298 gd->arch.sdhc_clk = usdhc_cfg.sdhc_clk; 299 300 return fsl_esdhc_initialize(bd, &usdhc_cfg); 301} 302#endif 303 304void board_init_f(ulong dummy) 305{ 306 ccgr_init(); 307 308 arch_cpu_init(); 309 310 gpr_init(); 311 312 /* setup GP timer */ 313 timer_init(); 314 315 displ5_set_iomux_uart_spl(); 316 317 /* UART clocks enabled and gd valid - init serial console */ 318 preloader_console_init(); 319 320 displ5_init_ecspi(); 321 322 /* DDR initialization */ 323 spl_dram_init(); 324 325 /* Clear the BSS. */ 326 memset(__bss_start, 0, __bss_end - __bss_start); 327 328 displ5_set_iomux_misc_spl(); 329 330 /* Initialize and reset WDT in SPL */ 331#ifdef CONFIG_SPL_WATCHDOG 332 hw_watchdog_init(); 333 schedule(); 334#endif 335 336 /* load/boot image from boot device */ 337 board_init_r(NULL, 0); 338} 339 340#define EM_PAD IMX_GPIO_NR(3, 29) 341int board_check_emergency_pad(void) 342{ 343 int ret; 344 345 ret = gpio_direction_input(EM_PAD); 346 if (ret) 347 return ret; 348 349 return !gpio_get_value(EM_PAD); 350} 351 352void board_boot_order(u32 *spl_boot_list) 353{ 354 /* Default boot sequence SPI -> MMC */ 355 spl_boot_list[0] = spl_boot_device(); 356 spl_boot_list[1] = BOOT_DEVICE_MMC1; 357 spl_boot_list[2] = BOOT_DEVICE_UART; 358 spl_boot_list[3] = BOOT_DEVICE_NONE; 359 360 /* 361 * In case of emergency PAD pressed, we always boot 362 * to proper u-boot and perform recovery tasks there. 363 */ 364 if (board_check_emergency_pad()) 365 return; 366 367#ifdef CONFIG_SPL_ENV_SUPPORT 368 /* 'fastboot' */ 369 const char *s; 370 371 if (env_init() || env_load()) 372 return; 373 374 s = env_get("BOOT_FROM"); 375 if (s && !bootcount_error() && strcmp(s, "ACTIVE") == 0) { 376 spl_boot_list[0] = BOOT_DEVICE_MMC1; 377 spl_boot_list[1] = spl_boot_device(); 378 } 379#endif 380} 381 382void reset_cpu(void) {} 383 384#ifdef CONFIG_SPL_LOAD_FIT 385int board_fit_config_name_match(const char *name) 386{ 387 return 0; 388} 389#endif 390 391#ifdef CONFIG_SPL_OS_BOOT 392/* Return: 1 - boot to U-Boot. 0 - boot OS (falcon mode) */ 393int spl_start_uboot(void) 394{ 395 /* break into full u-boot on 'c' */ 396 if (serial_tstc() && serial_getc() == 'c') 397 return 1; 398 399#ifdef CONFIG_SPL_ENV_SUPPORT 400 if (env_get_yesno("boot_os") != 1) 401 return 1; 402#endif 403 return 0; 404} 405#endif 406