1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * K+P iMX6Q KP_IMX6Q_TPC board configuration 4 * 5 * Copyright (C) 2018 Lukasz Majewski <lukma@denx.de> 6 */ 7 8#include <common.h> 9#include <init.h> 10#include <log.h> 11#include <asm/arch/clock.h> 12#include <asm/arch/crm_regs.h> 13#include <asm/arch/imx-regs.h> 14#include <asm/arch/mx6-ddr.h> 15#include <asm/arch/sys_proto.h> 16#include <asm/global_data.h> 17#include <asm/sections.h> 18#include <asm/io.h> 19#include <errno.h> 20#include <spl.h> 21#include <linux/delay.h> 22 23DECLARE_GLOBAL_DATA_PTR; 24 25static void ccgr_init(void) 26{ 27 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 28 29 writel(0x00C03F3F, &ccm->CCGR0); 30 writel(0x0030FC03, &ccm->CCGR1); 31 writel(0x0FFFC000, &ccm->CCGR2); 32 writel(0x3FF00000, &ccm->CCGR3); 33 writel(0x00FFF300, &ccm->CCGR4); 34 writel(0x0F0000C3, &ccm->CCGR5); 35 writel(0x000003FF, &ccm->CCGR6); 36} 37 38/* DDR3 */ 39static const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = { 40 .dram_sdclk_0 = 0x00000030, 41 .dram_sdclk_1 = 0x00000030, 42 .dram_cas = 0x00000030, 43 .dram_ras = 0x00000030, 44 .dram_reset = 0x00000030, 45 .dram_sdcke0 = 0x00003000, 46 .dram_sdcke1 = 0x00003000, 47 .dram_sdba2 = 0x00000000, 48 .dram_sdodt0 = 0x00000030, 49 .dram_sdodt1 = 0x00000030, 50 51 .dram_sdqs0 = 0x00000018, 52 .dram_sdqs1 = 0x00000018, 53 .dram_sdqs2 = 0x00000018, 54 .dram_sdqs3 = 0x00000018, 55 .dram_sdqs4 = 0x00000018, 56 .dram_sdqs5 = 0x00000018, 57 .dram_sdqs6 = 0x00000018, 58 .dram_sdqs7 = 0x00000018, 59 60 .dram_dqm0 = 0x00000018, 61 .dram_dqm1 = 0x00000018, 62 .dram_dqm2 = 0x00000018, 63 .dram_dqm3 = 0x00000018, 64 .dram_dqm4 = 0x00000018, 65 .dram_dqm5 = 0x00000018, 66 .dram_dqm6 = 0x00000018, 67 .dram_dqm7 = 0x00000018, 68}; 69 70static const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = { 71 .grp_ddr_type = 0x000c0000, 72 .grp_ddrmode_ctl = 0x00020000, 73 .grp_ddrpke = 0x00000000, 74 .grp_addds = 0x00000030, 75 .grp_ctlds = 0x00000030, 76 .grp_ddrmode = 0x00020000, 77 .grp_b0ds = 0x00000018, 78 .grp_b1ds = 0x00000018, 79 .grp_b2ds = 0x00000018, 80 .grp_b3ds = 0x00000018, 81 .grp_b4ds = 0x00000018, 82 .grp_b5ds = 0x00000018, 83 .grp_b6ds = 0x00000018, 84 .grp_b7ds = 0x00000018, 85}; 86 87static const struct mx6_mmdc_calibration mx6_4x256mx16_mmdc_calib = { 88 .p0_mpwldectrl0 = 0x001F001F, 89 .p0_mpwldectrl1 = 0x001F001F, 90 .p1_mpwldectrl0 = 0x001F001F, 91 .p1_mpwldectrl1 = 0x001F001F, 92 .p0_mpdgctrl0 = 0x43270338, 93 .p0_mpdgctrl1 = 0x03200314, 94 .p1_mpdgctrl0 = 0x431A032F, 95 .p1_mpdgctrl1 = 0x03200263, 96 .p0_mprddlctl = 0x4B434748, 97 .p1_mprddlctl = 0x4445404C, 98 .p0_mpwrdlctl = 0x38444542, 99 .p1_mpwrdlctl = 0x4935493A, 100}; 101 102/* MT41K256M16 (4Gb density) */ 103static const struct mx6_ddr3_cfg mt41k256m16 = { 104 .mem_speed = 1600, 105 .density = 4, 106 .width = 16, 107 .banks = 8, 108 .rowaddr = 15, 109 .coladdr = 10, 110 .pagesz = 2, 111 .trcd = 1375, 112 .trcmin = 4875, 113 .trasmin = 3500, 114}; 115 116#ifdef CONFIG_MX6_DDRCAL 117static void spl_dram_print_cal(struct mx6_ddr_sysinfo const *sysinfo) 118{ 119 struct mx6_mmdc_calibration calibration = {0}; 120 121 mmdc_read_calibration(sysinfo, &calibration); 122 123 debug(".p0_mpdgctrl0\t= 0x%08X\n", calibration.p0_mpdgctrl0); 124 debug(".p0_mpdgctrl1\t= 0x%08X\n", calibration.p0_mpdgctrl1); 125 debug(".p0_mprddlctl\t= 0x%08X\n", calibration.p0_mprddlctl); 126 debug(".p0_mpwrdlctl\t= 0x%08X\n", calibration.p0_mpwrdlctl); 127 debug(".p0_mpwldectrl0\t= 0x%08X\n", calibration.p0_mpwldectrl0); 128 debug(".p0_mpwldectrl1\t= 0x%08X\n", calibration.p0_mpwldectrl1); 129 debug(".p1_mpdgctrl0\t= 0x%08X\n", calibration.p1_mpdgctrl0); 130 debug(".p1_mpdgctrl1\t= 0x%08X\n", calibration.p1_mpdgctrl1); 131 debug(".p1_mprddlctl\t= 0x%08X\n", calibration.p1_mprddlctl); 132 debug(".p1_mpwrdlctl\t= 0x%08X\n", calibration.p1_mpwrdlctl); 133 debug(".p1_mpwldectrl0\t= 0x%08X\n", calibration.p1_mpwldectrl0); 134 debug(".p1_mpwldectrl1\t= 0x%08X\n", calibration.p1_mpwldectrl1); 135} 136 137static void spl_dram_perform_cal(struct mx6_ddr_sysinfo const *sysinfo) 138{ 139 int ret; 140 141 /* Perform DDR DRAM calibration */ 142 udelay(100); 143 ret = mmdc_do_write_level_calibration(sysinfo); 144 if (ret) { 145 printf("DDR: Write level calibration error [%d]\n", ret); 146 return; 147 } 148 149 ret = mmdc_do_dqs_calibration(sysinfo); 150 if (ret) { 151 printf("DDR: DQS calibration error [%d]\n", ret); 152 return; 153 } 154 155 spl_dram_print_cal(sysinfo); 156} 157#endif /* CONFIG_MX6_DDRCAL */ 158 159static void spl_dram_init(void) 160{ 161 struct mx6_ddr_sysinfo sysinfo = { 162 /* width of data bus:0=16,1=32,2=64 */ 163 .dsize = 2, 164 /* config for full 4GB range so that get_mem_size() works */ 165 .cs_density = 32, /* 32Gb per CS */ 166 /* single chip select */ 167 .ncs = 1, 168 .cs1_mirror = 0, 169 .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */ 170 .rtt_nom = 2 /*DDR3_RTT_120_OHM*/, /* RTT_Nom = RZQ/2 */ 171 .walat = 1, /* Write additional latency */ 172 .ralat = 5, /* Read additional latency */ 173 .mif3_mode = 3, /* Command prediction working mode */ 174 .bi_on = 1, /* Bank interleaving enabled */ 175 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ 176 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ 177 .pd_fast_exit = 1, /* enable precharge power-down fast exit */ 178 .ddr_type = DDR_TYPE_DDR3, 179 .refsel = 1, /* Refresh cycles at 32KHz */ 180 .refr = 7, /* 8 refresh commands per refresh cycle */ 181 }; 182 183 mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs); 184 mx6_dram_cfg(&sysinfo, &mx6_4x256mx16_mmdc_calib, &mt41k256m16); 185 186#ifdef CONFIG_MX6_DDRCAL 187 spl_dram_perform_cal(&sysinfo); 188#endif 189} 190 191void board_boot_order(u32 *spl_boot_list) 192{ 193 u32 boot_device = spl_boot_device(); 194 u32 reg = imx6_src_get_boot_mode(); 195 196 reg = (reg & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT; 197 198 debug("%s: boot device: 0x%x (0x4 SD, 0x6 eMMC)\n", __func__, reg); 199 if (boot_device == BOOT_DEVICE_MMC1) 200 if (reg == IMX6_BMODE_MMC || reg == IMX6_BMODE_EMMC) 201 boot_device = BOOT_DEVICE_MMC2; 202 203 spl_boot_list[0] = boot_device; 204 /* 205 * Below boot device is a 'fallback' - it shall always be possible to 206 * boot from SD card 207 */ 208 spl_boot_list[1] = BOOT_DEVICE_MMC1; 209} 210 211void board_init_f(ulong dummy) 212{ 213 /* setup AIPS and disable watchdog */ 214 arch_cpu_init(); 215 216 ccgr_init(); 217 gpr_init(); 218 219 /* setup GP timer */ 220 timer_init(); 221 222 /* Early - pre reloc - driver model setup */ 223 spl_early_init(); 224 225 /* UART clocks enabled and gd valid - init serial console */ 226 preloader_console_init(); 227 228 /* DDR initialization */ 229 spl_dram_init(); 230 231 /* Clear the BSS. */ 232 memset(__bss_start, 0, __bss_end - __bss_start); 233} 234