1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (C) 2018 Kontron Electronics GmbH 4 */ 5 6#include <asm/arch/clock.h> 7#include <asm/arch/crm_regs.h> 8#include <asm/arch/mx6-pins.h> 9#include <asm/arch/sys_proto.h> 10#include <asm/global_data.h> 11#include <asm/gpio.h> 12#include <asm/io.h> 13#include <asm/mach-imx/iomux-v3.h> 14#include <asm/sections.h> 15#include <fsl_esdhc_imx.h> 16#include <init.h> 17#include <linux/delay.h> 18#include <linux/sizes.h> 19#include <linux/errno.h> 20#include <mmc.h> 21#include <sl-mx6ul-common.h> 22 23DECLARE_GLOBAL_DATA_PTR; 24 25enum { 26 BOARD_TYPE_KTN_SL_UL = 1, 27 BOARD_TYPE_KTN_SL_ULL, 28 BOARD_TYPE_MAX 29}; 30 31#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 32 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 33 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 34 35#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 36 PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ 37 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 38 39#define USDHC_CD_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 40 PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_LOW | \ 41 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 42 43#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \ 44 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) 45 46#include <spl.h> 47#include <asm/arch/mx6-ddr.h> 48 49static iomux_v3_cfg_t const usdhc1_pads[] = { 50 MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 51 MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 52 MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 53 MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 54 MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 55 MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 56 57 /* CD */ 58 MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(USDHC_CD_PAD_CTRL), 59}; 60 61#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 19) 62 63static iomux_v3_cfg_t const usdhc2_pads[] = { 64 MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 65 MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 66 MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 67 MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 68 MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 69 MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 70 /* RST */ 71 MX6_PAD_NAND_ALE__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), 72}; 73 74#define USDHC2_PWR_GPIO IMX_GPIO_NR(4, 10) 75 76static struct fsl_esdhc_cfg usdhc_cfg[2] = { 77 {USDHC1_BASE_ADDR, 0, 4}, 78 {USDHC2_BASE_ADDR, 0, 4}, 79}; 80 81int board_mmc_getcd(struct mmc *mmc) 82{ 83 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 84 int ret = 0; 85 86 switch (cfg->esdhc_base) { 87 case USDHC1_BASE_ADDR: 88 ret = !gpio_get_value(USDHC1_CD_GPIO); 89 break; 90 case USDHC2_BASE_ADDR: 91 // This SDHC interface does not use a CD pin 92 ret = 1; 93 break; 94 } 95 96 return ret; 97} 98 99int board_mmc_init(struct bd_info *bis) 100{ 101 int i, ret; 102 103 /* 104 * According to the board_mmc_init() the following map is done: 105 * (U-Boot device node) (Physical Port) 106 * mmc0 USDHC1 107 * mmc1 USDHC2 108 */ 109 for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) { 110 switch (i) { 111 case 0: 112 imx_iomux_v3_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); 113 gpio_direction_input(USDHC1_CD_GPIO); 114 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); 115 break; 116 case 1: 117 imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); 118 gpio_direction_output(USDHC2_PWR_GPIO, 0); 119 udelay(500); 120 gpio_direction_output(USDHC2_PWR_GPIO, 1); 121 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); 122 break; 123 default: 124 printf("Warning: you configured more USDHC controllers (%d) than supported by the board\n", 125 i + 1); 126 return -EINVAL; 127 } 128 129 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); 130 if (ret) { 131 printf("Warning: failed to initialize mmc dev %d\n", i); 132 return ret; 133 } 134 } 135 return 0; 136} 137 138iomux_v3_cfg_t const ecspi2_pads[] = { 139 MX6_PAD_CSI_DATA00__ECSPI2_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), 140 MX6_PAD_CSI_DATA02__ECSPI2_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), 141 MX6_PAD_CSI_DATA03__ECSPI2_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), 142 MX6_PAD_CSI_DATA01__GPIO4_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL), 143}; 144 145int board_spi_cs_gpio(unsigned int bus, unsigned int cs) 146{ 147 return (bus == CONFIG_SF_DEFAULT_BUS && cs == CONFIG_SF_DEFAULT_CS) 148 ? (IMX_GPIO_NR(4, 22)) : -1; 149} 150 151static void setup_spi(void) 152{ 153 gpio_request(IMX_GPIO_NR(4, 22), "spi2_cs0"); 154 gpio_direction_output(IMX_GPIO_NR(4, 22), 1); 155 imx_iomux_v3_setup_multiple_pads(ecspi2_pads, ARRAY_SIZE(ecspi2_pads)); 156 157 enable_spi_clk(true, 1); 158} 159 160static iomux_v3_cfg_t const uart4_pads[] = { 161 MX6_PAD_UART4_TX_DATA__UART4_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), 162 MX6_PAD_UART4_RX_DATA__UART4_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), 163}; 164 165static void setup_iomux_uart(void) 166{ 167 imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads)); 168} 169 170// DDR 256MB (Hynix H5TQ2G63DFR) 171static struct mx6_ddr3_cfg mem_256M_ddr = { 172 .mem_speed = 800, 173 .density = 2, 174 .width = 16, 175 .banks = 8, 176 .rowaddr = 14, 177 .coladdr = 10, 178 .pagesz = 2, 179 .trcd = 1350, 180 .trcmin = 4950, 181 .trasmin = 3600, 182}; 183 184static struct mx6_mmdc_calibration mx6_mmcd_256M_calib = { 185 .p0_mpwldectrl0 = 0x00000000, 186 .p0_mpdgctrl0 = 0x01340134, 187 .p0_mprddlctl = 0x40405052, 188 .p0_mpwrdlctl = 0x40404E48, 189}; 190 191// DDR 512MB (Hynix H5TQ4G63DFR) 192static struct mx6_ddr3_cfg mem_512M_ddr = { 193 .mem_speed = 800, 194 .density = 4, 195 .width = 16, 196 .banks = 8, 197 .rowaddr = 15, 198 .coladdr = 10, 199 .pagesz = 2, 200 .trcd = 1350, 201 .trcmin = 4950, 202 .trasmin = 3600, 203}; 204 205static struct mx6_mmdc_calibration mx6_mmcd_512M_calib = { 206 .p0_mpwldectrl0 = 0x00000000, 207 .p0_mpdgctrl0 = 0X01440144, 208 .p0_mprddlctl = 0x40405454, 209 .p0_mpwrdlctl = 0x40404E4C, 210}; 211 212// Common DDR parameters (256MB and 512MB) 213static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = { 214 .grp_addds = 0x00000028, 215 .grp_ddrmode_ctl = 0x00020000, 216 .grp_b0ds = 0x00000028, 217 .grp_ctlds = 0x00000028, 218 .grp_b1ds = 0x00000028, 219 .grp_ddrpke = 0x00000000, 220 .grp_ddrmode = 0x00020000, 221 .grp_ddr_type = 0x000c0000, 222}; 223 224static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = { 225 .dram_dqm0 = 0x00000028, 226 .dram_dqm1 = 0x00000028, 227 .dram_ras = 0x00000028, 228 .dram_cas = 0x00000028, 229 .dram_odt0 = 0x00000028, 230 .dram_odt1 = 0x00000028, 231 .dram_sdba2 = 0x00000000, 232 .dram_sdclk_0 = 0x00000028, 233 .dram_sdqs0 = 0x00000028, 234 .dram_sdqs1 = 0x00000028, 235 .dram_reset = 0x00000028, 236}; 237 238struct mx6_ddr_sysinfo ddr_sysinfo = { 239 .dsize = 0, 240 .cs_density = 20, 241 .ncs = 1, 242 .cs1_mirror = 0, 243 .rtt_wr = 2, 244 .rtt_nom = 1, /* RTT_Nom = RZQ/2 */ 245 .walat = 1, /* Write additional latency */ 246 .ralat = 5, /* Read additional latency */ 247 .mif3_mode = 3, /* Command prediction working mode */ 248 .bi_on = 1, /* Bank interleaving enabled */ 249 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ 250 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ 251 .ddr_type = DDR_TYPE_DDR3, 252 .refsel = 0, /* Refresh cycles at 64KHz */ 253 .refr = 1, /* 2 refresh commands per refresh cycle */ 254}; 255 256static void ccgr_init(void) 257{ 258 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 259 260 writel(0xFFFFFFFF, &ccm->CCGR0); 261 writel(0xFFFFFFFF, &ccm->CCGR1); 262 writel(0xFFFFFFFF, &ccm->CCGR2); 263 writel(0xFFFFFFFF, &ccm->CCGR3); 264 writel(0xFFFFFFFF, &ccm->CCGR4); 265 writel(0xFFFFFFFF, &ccm->CCGR5); 266 writel(0xFFFFFFFF, &ccm->CCGR6); 267 writel(0xFFFFFFFF, &ccm->CCGR7); 268} 269 270static void spl_dram_init(void) 271{ 272 unsigned int size; 273 274 // DDR RAM connection is always 16 bit wide. Init IOs. 275 mx6ul_dram_iocfg(16, &mx6_ddr_ioregs, &mx6_grp_ioregs); 276 277 // Try to detect the 512MB RAM chip first. 278 mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_512M_calib, &mem_512M_ddr); 279 280 // Get the available RAM size 281 size = get_ram_size((void *)PHYS_SDRAM, SZ_512M); 282 283 gd->ram_size = size; 284 285 if (size == SZ_512M) { 286 // 512MB RAM was detected 287 return; 288 } else if (size == SZ_256M) { 289 // 256MB RAM was detected, use correct config and calibration 290 mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_256M_calib, &mem_256M_ddr); 291 } else { 292 printf("Invalid DDR RAM size detected: %x\n", size); 293 } 294} 295 296static int do_board_detect(void) 297{ 298 if (is_mx6ul()) 299 gd->board_type = BOARD_TYPE_KTN_SL_UL; 300 else if (is_mx6ull()) 301 gd->board_type = BOARD_TYPE_KTN_SL_ULL; 302 303 printf("Kontron SL i.MX6UL%s (N6%s1x) module, %lu MB RAM detected\n", 304 is_mx6ull() ? "L" : "", is_mx6ull() ? "4" : "3", gd->ram_size / SZ_1M); 305 306 return 0; 307} 308 309void board_init_f(ulong dummy) 310{ 311 ccgr_init(); 312 313 /* setup AIPS and disable watchdog */ 314 arch_cpu_init(); 315 316 /* iomux and setup of UART and SPI */ 317 board_early_init_f(); 318 319 /* setup GP timer */ 320 timer_init(); 321 322 /* UART clocks enabled and gd valid - init serial console */ 323 preloader_console_init(); 324 325 /* DDR initialization */ 326 spl_dram_init(); 327 328 /* Clear the BSS. */ 329 memset(__bss_start, 0, __bss_end - __bss_start); 330 331 /* Detect the board type */ 332 do_board_detect(); 333 334 /* load/boot image from boot device */ 335 board_init_r(NULL, 0); 336} 337 338void board_boot_order(u32 *spl_boot_list) 339{ 340 u32 bootdev = spl_boot_device(); 341 342 /* 343 * The default boot fuse settings use the SD card (MMC1) as primary 344 * boot device, but allow SPI NOR as a fallback boot device. There 345 * is no proper way to detect if the fallback was used. Therefore 346 * we read the ECSPI2_CONREG register and see if it differs from the 347 * reset value 0x0. If that's the case we can assume that the BootROM 348 * has successfully probed the SPI NOR. 349 */ 350 switch (bootdev) { 351 case BOOT_DEVICE_MMC1: 352 case BOOT_DEVICE_MMC2: 353 if (sl_mx6ul_is_spi_nor_boot()) { 354 spl_boot_list[0] = BOOT_DEVICE_SPI; 355 return; 356 } 357 break; 358 } 359 360 spl_boot_list[0] = bootdev; 361} 362 363int board_early_init_f(void) 364{ 365 setup_iomux_uart(); 366 if (sl_mx6ul_is_spi_nor_boot()) 367 setup_spi(); 368 369 return 0; 370} 371 372int board_fit_config_name_match(const char *name) 373{ 374 if (gd->board_type == BOARD_TYPE_KTN_SL_UL && is_mx6ul() && 375 (!strcmp(name, "imx6ul-kontron-n631x-s") || !strcmp(name, "imx6ul-kontron-bl"))) 376 return 0; 377 378 if (gd->board_type == BOARD_TYPE_KTN_SL_ULL && is_mx6ull() && 379 (!strcmp(name, "imx6ull-kontron-n641x-s") || !strcmp(name, "imx6ull-kontron-bl"))) 380 return 0; 381 382 return -1; 383} 384