Searched refs:dram_timing_info (Results 1 - 25 of 78) sorted by relevance

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/u-boot/board/technexion/pico-imx8mq/
H A Dlpddr4_timing.h9 extern struct dram_timing_info dram_timing_1gb;
10 extern struct dram_timing_info dram_timing_2gb;
11 extern struct dram_timing_info dram_timing_3gb;
12 extern struct dram_timing_info dram_timing_4gb;
H A Dspl.c53 struct dram_timing_info *dram_timing;
/u-boot/board/gateworks/venice/
H A Dlpddr4_timing.h10 extern struct dram_timing_info dram_timing_512mb;
11 extern struct dram_timing_info dram_timing_1gb;
12 extern struct dram_timing_info dram_timing_2gb;
13 extern struct dram_timing_info dram_timing_4gb;
15 extern struct dram_timing_info dram_timing_1gb_single_die;
16 extern struct dram_timing_info dram_timing_2gb_single_die;
17 extern struct dram_timing_info dram_timing_2gb_dual_die;
19 extern struct dram_timing_info dram_timing_1gb_single_die;
20 extern struct dram_timing_info dram_timing_4gb_dual_die;
H A Dspl.c38 struct dram_timing_info *dram_timing;
/u-boot/board/data_modul/imx8mm_edm_sbc/
H A Dlpddr4_timing.h9 extern struct dram_timing_info dmo_imx8mm_sbc_dram_timing_16_32;
10 extern struct dram_timing_info dmo_imx8mm_sbc_dram_timing_32_32;
H A Dspl.c84 static struct dram_timing_info *dram_timing_info[8] = { variable in typeref:struct:dram_timing_info
97 dmo_board_init_f(IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B, dram_timing_info);
/u-boot/board/data_modul/imx8mp_edm_sbc/
H A Dlpddr4_timing.h9 extern struct dram_timing_info dmo_imx8mp_sbc_dram_timing_32_32;
H A Dspl.c142 static struct dram_timing_info *dram_timing_info[8] = { variable in typeref:struct:dram_timing_info
155 dmo_board_init_f(MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B, dram_timing_info);
/u-boot/board/dhelectronics/dh_imx8mp/
H A Dlpddr4_timing.h9 extern struct dram_timing_info dh_imx8mp_dhcom_dram_timing_16g_x32;
10 extern struct dram_timing_info dh_imx8mp_dhcom_dram_timing_32g_x32;
H A Dspl.c110 static struct dram_timing_info *dram_timing_info[8] = { variable in typeref:struct:dram_timing_info
129 if (!dram_timing_info[memcfg]) {
132 for (i = 0; i < ARRAY_SIZE(dram_timing_info); i++)
133 if (dram_timing_info[i]) /* Configuration found */
137 ddr_init(dram_timing_info[memcfg]);
/u-boot/board/data_modul/common/
H A Dcommon.h14 struct dram_timing_info *dram_timing_info[8]);
H A Dcommon.c91 static void spl_dram_init(struct dram_timing_info *dram_timing_info[8]) argument
103 if (!dram_timing_info[memcfg]) {
107 if (dram_timing_info[i]) /* Configuration found */
111 ddr_init(dram_timing_info[memcfg]);
121 struct dram_timing_info *dram_timing_info[8])
158 spl_dram_init(dram_timing_info);
120 dmo_board_init_f(const iomux_v3_cfg_t wdog_pad, struct dram_timing_info *dram_timing_info[8]) argument
/u-boot/board/compulab/imx8mm-cl-iot-gate/ddr/
H A Dddr.h11 extern struct dram_timing_info ucm_dram_timing_ff020008;
12 extern struct dram_timing_info ucm_dram_timing_ff000110;
13 extern struct dram_timing_info ucm_dram_timing_01061010;
H A Dddr.c42 struct dram_timing_info *timing;
/u-boot/arch/arm/include/asm/arch-imx9/
H A Dddr.h78 struct dram_timing_info { struct
101 extern struct dram_timing_info dram_timing;
104 int ddr_init(struct dram_timing_info *timing_info);
105 int ddr_cfg_phy(struct dram_timing_info *timing_info);
108 void *dram_config_save(struct dram_timing_info *info, unsigned long base);
/u-boot/drivers/ddr/imx/phy/
H A Dddrphy_train.c12 int ddr_cfg_phy(struct dram_timing_info *dram_timing)
H A Dhelper.c177 void *dram_config_save(struct dram_timing_info *timing_info, unsigned long saved_timing_base)
180 struct dram_timing_info *saved_timing = (struct dram_timing_info *)saved_timing_base;
/u-boot/board/kontron/pitx_imx8m/
H A Dspl.c26 extern struct dram_timing_info dram_timing_2gb;
27 extern struct dram_timing_info dram_timing_4gb;
34 struct dram_timing_info *dram_timing;
/u-boot/drivers/ddr/imx/imx9/
H A Dddr_init.c74 void ddrc_config(struct dram_timing_info *dram_timing)
173 void update_umctl2_rank_space_setting(struct dram_timing_info *dram_timing, unsigned int pstat_num)
338 int ddr_init(struct dram_timing_info *dram_timing)
341 struct dram_timing_info *saved_timing;
394 saved_timing = (struct dram_timing_info *)CONFIG_SAVED_DRAM_TIMING_BASE;
/u-boot/board/purism/librem5/
H A Dlibrem5.h179 extern struct dram_timing_info dram_timing_b0;
/u-boot/board/mntre/imx8mq_reform2/
H A Dspl.c33 extern struct dram_timing_info dram_timing_ch2;
/u-boot/board/freescale/imx8mq_evk/
H A Dspl.c35 extern struct dram_timing_info dram_timing_b0;
/u-boot/arch/arm/include/asm/arch-imx8m/
H A Dddr.h685 struct dram_timing_info { struct
705 extern struct dram_timing_info dram_timing;
708 int ddr_init(struct dram_timing_info *timing_info);
709 int ddr_cfg_phy(struct dram_timing_info *timing_info);
712 void *dram_config_save(struct dram_timing_info *info, unsigned long base);
/u-boot/drivers/ddr/imx/imx8m/
H A Dddr_init.c314 int ddr_init(struct dram_timing_info *dram_timing)
/u-boot/board/variscite/imx8mn_var_som/
H A Dddr4_timing.c518 struct dram_timing_info dram_timing = {

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