1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2018, 2021 NXP
4 *
5 */
6
7#include <common.h>
8#include <hang.h>
9#include <image.h>
10#include <init.h>
11#include <log.h>
12#include <asm/global_data.h>
13#include <asm/io.h>
14#include <errno.h>
15#include <asm/io.h>
16#include <asm/arch/ddr.h>
17#include <asm/arch/imx8mq_pins.h>
18#include <asm/arch/sys_proto.h>
19#include <asm/arch/clock.h>
20#include <asm/mach-imx/iomux-v3.h>
21#include <asm/mach-imx/gpio.h>
22#include <asm/mach-imx/mxc_i2c.h>
23#include <asm/sections.h>
24#include <fsl_esdhc_imx.h>
25#include <fsl_sec.h>
26#include <mmc.h>
27#include <linux/delay.h>
28#include <power/pmic.h>
29#include <power/pfuze100_pmic.h>
30#include <spl.h>
31#include "../common/pfuze.h"
32
33DECLARE_GLOBAL_DATA_PTR;
34
35extern struct dram_timing_info dram_timing_b0;
36
37static void spl_dram_init(void)
38{
39	/* ddr init */
40	if (soc_rev() >= CHIP_REV_2_1)
41		ddr_init(&dram_timing);
42	else
43		ddr_init(&dram_timing_b0);
44}
45
46#define I2C_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
47#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
48static struct i2c_pads_info i2c_pad_info1 = {
49	.scl = {
50		.i2c_mode = IMX8MQ_PAD_I2C1_SCL__I2C1_SCL | PC,
51		.gpio_mode = IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 | PC,
52		.gp = IMX_GPIO_NR(5, 14),
53	},
54	.sda = {
55		.i2c_mode = IMX8MQ_PAD_I2C1_SDA__I2C1_SDA | PC,
56		.gpio_mode = IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 | PC,
57		.gp = IMX_GPIO_NR(5, 15),
58	},
59};
60
61#define USDHC2_CD_GPIO	IMX_GPIO_NR(2, 12)
62#define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10)
63#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19)
64
65int board_mmc_getcd(struct mmc *mmc)
66{
67	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
68	int ret = 0;
69
70	switch (cfg->esdhc_base) {
71	case USDHC1_BASE_ADDR:
72		ret = 1;
73		break;
74	case USDHC2_BASE_ADDR:
75		ret = !gpio_get_value(USDHC2_CD_GPIO);
76		return ret;
77	}
78
79	return 1;
80}
81
82#define USDHC_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \
83			 PAD_CTL_FSEL2)
84#define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1)
85
86static iomux_v3_cfg_t const usdhc1_pads[] = {
87	IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
88	IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
89	IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
90	IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
91	IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
92	IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
93	IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
94	IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
95	IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
96	IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
97	IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
98};
99
100static iomux_v3_cfg_t const usdhc2_pads[] = {
101	IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
102	IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
103	IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
104	IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
105	IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0x16 */
106	IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
107	IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
108	IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
109};
110
111static struct fsl_esdhc_cfg usdhc_cfg[2] = {
112	{USDHC1_BASE_ADDR, 0, 8},
113	{USDHC2_BASE_ADDR, 0, 4},
114};
115
116int board_mmc_init(struct bd_info *bis)
117{
118	int i, ret;
119	/*
120	 * According to the board_mmc_init() the following map is done:
121	 * (U-Boot device node)    (Physical Port)
122	 * mmc0                    USDHC1
123	 * mmc1                    USDHC2
124	 */
125	for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) {
126		switch (i) {
127		case 0:
128			init_clk_usdhc(0);
129			usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT);
130			imx_iomux_v3_setup_multiple_pads(usdhc1_pads,
131							 ARRAY_SIZE(usdhc1_pads));
132			gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset");
133			gpio_direction_output(USDHC1_PWR_GPIO, 0);
134			udelay(500);
135			gpio_direction_output(USDHC1_PWR_GPIO, 1);
136			break;
137		case 1:
138			init_clk_usdhc(1);
139			usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT);
140			imx_iomux_v3_setup_multiple_pads(usdhc2_pads,
141							 ARRAY_SIZE(usdhc2_pads));
142			gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset");
143			gpio_direction_output(USDHC2_PWR_GPIO, 0);
144			udelay(500);
145			gpio_direction_output(USDHC2_PWR_GPIO, 1);
146			break;
147		default:
148			printf("Warning: you configured more USDHC controllers(%d) than supported by the board\n", i + 1);
149			return -EINVAL;
150		}
151
152		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
153		if (ret)
154			return ret;
155	}
156
157	return 0;
158}
159
160#if CONFIG_IS_ENABLED(POWER_LEGACY)
161#define I2C_PMIC	0
162int power_init_board(void)
163{
164	struct pmic *p;
165	int ret;
166	unsigned int reg;
167
168	ret = power_pfuze100_init(I2C_PMIC);
169	if (ret)
170		return -ENODEV;
171
172	p = pmic_get("PFUZE100");
173	ret = pmic_probe(p);
174	if (ret)
175		return -ENODEV;
176
177	pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
178	printf("PMIC:  PFUZE100 ID=0x%02x\n", reg);
179
180	pmic_reg_read(p, PFUZE100_SW3AVOL, &reg);
181	if ((reg & 0x3f) != 0x18) {
182		reg &= ~0x3f;
183		reg |= 0x18;
184		pmic_reg_write(p, PFUZE100_SW3AVOL, reg);
185	}
186
187	ret = pfuze_mode_init(p, APS_PFM);
188	if (ret < 0)
189		return ret;
190
191	/* set SW3A standby mode to off */
192	pmic_reg_read(p, PFUZE100_SW3AMODE, &reg);
193	reg &= ~0xf;
194	reg |= APS_OFF;
195	pmic_reg_write(p, PFUZE100_SW3AMODE, reg);
196
197	return 0;
198}
199#endif
200
201void spl_board_init(void)
202{
203	if (IS_ENABLED(CONFIG_FSL_CAAM)) {
204		if (sec_init())
205			printf("\nsec_init failed!\n");
206	}
207	puts("Normal Boot\n");
208}
209
210#ifdef CONFIG_SPL_LOAD_FIT
211int board_fit_config_name_match(const char *name)
212{
213	/* Just empty function now - can't decide what to choose */
214	debug("%s: %s\n", __func__, name);
215
216	return 0;
217}
218#endif
219
220void board_init_f(ulong dummy)
221{
222	int ret;
223
224	/* Clear global data */
225	memset((void *)gd, 0, sizeof(gd_t));
226
227	arch_cpu_init();
228
229	init_uart_clk(0);
230
231	board_early_init_f();
232
233	timer_init();
234
235	preloader_console_init();
236
237	/* Clear the BSS. */
238	memset(__bss_start, 0, __bss_end - __bss_start);
239
240	ret = spl_init();
241	if (ret) {
242		debug("spl_init() failed: %d\n", ret);
243		hang();
244	}
245
246	enable_tzc380();
247
248	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
249
250	power_init_board();
251
252	/* DDR initialization */
253	spl_dram_init();
254
255	board_init_r(NULL, 0);
256}
257