1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright 2018 NXP 4 */ 5 6#include <common.h> 7#include <binman_sym.h> 8#include <log.h> 9#include <spl.h> 10#include <asm/global_data.h> 11#include <asm/io.h> 12#include <errno.h> 13#include <asm/io.h> 14#include <asm/arch/ddr.h> 15#include <asm/arch/ddr.h> 16#include <asm/sections.h> 17 18DECLARE_GLOBAL_DATA_PTR; 19 20#define IMEM_LEN 32768 /* byte */ 21#define DMEM_LEN 16384 /* byte */ 22#define IMEM_2D_OFFSET 49152 23 24#define IMEM_OFFSET_ADDR 0x00050000 25#define DMEM_OFFSET_ADDR 0x00054000 26#define DDR_TRAIN_CODE_BASE_ADDR IP2APB_DDRPHY_IPS_BASE_ADDR(0) 27 28binman_sym_declare(ulong, ddr_1d_imem_fw, image_pos); 29binman_sym_declare(ulong, ddr_1d_imem_fw, size); 30 31binman_sym_declare(ulong, ddr_1d_dmem_fw, image_pos); 32binman_sym_declare(ulong, ddr_1d_dmem_fw, size); 33 34#if !IS_ENABLED(CONFIG_IMX8M_DDR3L) 35binman_sym_declare(ulong, ddr_2d_imem_fw, image_pos); 36binman_sym_declare(ulong, ddr_2d_imem_fw, size); 37 38binman_sym_declare(ulong, ddr_2d_dmem_fw, image_pos); 39binman_sym_declare(ulong, ddr_2d_dmem_fw, size); 40#endif 41 42/* We need PHY iMEM PHY is 32KB padded */ 43void ddr_load_train_firmware(enum fw_type type) 44{ 45 u32 tmp32, i; 46 u32 error = 0; 47 unsigned long pr_to32, pr_from32; 48 uint32_t fw_offset = type ? IMEM_2D_OFFSET : 0; 49 unsigned long imem_start = (unsigned long)_end + fw_offset; 50 unsigned long dmem_start; 51 unsigned long imem_len = IMEM_LEN, dmem_len = DMEM_LEN; 52 static enum fw_type last_type = -1; 53 54 /* If FW doesn't change, we can save the loading. */ 55 if (last_type == type) 56 return; 57 58 last_type = type; 59 60#ifdef CONFIG_SPL_OF_CONTROL 61 if (gd->fdt_blob && !fdt_check_header(gd->fdt_blob)) { 62 imem_start = roundup((unsigned long)_end + 63 fdt_totalsize(gd->fdt_blob), 4) + 64 fw_offset; 65 } 66#endif 67 68 dmem_start = imem_start + imem_len; 69 70 if (BINMAN_SYMS_OK) { 71 switch (type) { 72 case FW_1D_IMAGE: 73 imem_start = binman_sym(ulong, ddr_1d_imem_fw, image_pos); 74 imem_len = binman_sym(ulong, ddr_1d_imem_fw, size); 75 dmem_start = binman_sym(ulong, ddr_1d_dmem_fw, image_pos); 76 dmem_len = binman_sym(ulong, ddr_1d_dmem_fw, size); 77 break; 78 case FW_2D_IMAGE: 79#if !IS_ENABLED(CONFIG_IMX8M_DDR3L) 80 imem_start = binman_sym(ulong, ddr_2d_imem_fw, image_pos); 81 imem_len = binman_sym(ulong, ddr_2d_imem_fw, size); 82 dmem_start = binman_sym(ulong, ddr_2d_dmem_fw, image_pos); 83 dmem_len = binman_sym(ulong, ddr_2d_dmem_fw, size); 84#endif 85 break; 86 } 87 } 88 89 pr_from32 = imem_start; 90 pr_to32 = IMEM_OFFSET_ADDR; 91 for (i = 0x0; i < imem_len; ) { 92 tmp32 = readl(pr_from32); 93 writew(tmp32 & 0x0000ffff, DDR_TRAIN_CODE_BASE_ADDR + ddrphy_addr_remap(pr_to32)); 94 pr_to32 += 1; 95 writew((tmp32 >> 16) & 0x0000ffff, 96 DDR_TRAIN_CODE_BASE_ADDR + ddrphy_addr_remap(pr_to32)); 97 pr_to32 += 1; 98 pr_from32 += 4; 99 i += 4; 100 } 101 102 pr_from32 = dmem_start; 103 pr_to32 = DMEM_OFFSET_ADDR; 104 for (i = 0x0; i < dmem_len; ) { 105 tmp32 = readl(pr_from32); 106 writew(tmp32 & 0x0000ffff, DDR_TRAIN_CODE_BASE_ADDR + ddrphy_addr_remap(pr_to32)); 107 pr_to32 += 1; 108 writew((tmp32 >> 16) & 0x0000ffff, 109 DDR_TRAIN_CODE_BASE_ADDR + ddrphy_addr_remap(pr_to32)); 110 pr_to32 += 1; 111 pr_from32 += 4; 112 i += 4; 113 } 114 115 debug("check ddr_pmu_train_imem code\n"); 116 pr_from32 = imem_start; 117 pr_to32 = IMEM_OFFSET_ADDR; 118 for (i = 0x0; i < imem_len; ) { 119 tmp32 = (readw(DDR_TRAIN_CODE_BASE_ADDR + ddrphy_addr_remap(pr_to32)) & 0x0000ffff); 120 pr_to32 += 1; 121 tmp32 += ((readw(DDR_TRAIN_CODE_BASE_ADDR + 122 ddrphy_addr_remap(pr_to32)) & 0x0000ffff) << 16); 123 124 if (tmp32 != readl(pr_from32)) { 125 debug("%lx %lx\n", pr_from32, pr_to32); 126 error++; 127 } 128 pr_from32 += 4; 129 pr_to32 += 1; 130 i += 4; 131 } 132 if (error) 133 printf("check ddr_pmu_train_imem code fail=%d\n", error); 134 else 135 debug("check ddr_pmu_train_imem code pass\n"); 136 137 debug("check ddr4_pmu_train_dmem code\n"); 138 pr_from32 = dmem_start; 139 pr_to32 = DMEM_OFFSET_ADDR; 140 for (i = 0x0; i < dmem_len;) { 141 tmp32 = (readw(DDR_TRAIN_CODE_BASE_ADDR + ddrphy_addr_remap(pr_to32)) & 0x0000ffff); 142 pr_to32 += 1; 143 tmp32 += ((readw(DDR_TRAIN_CODE_BASE_ADDR + 144 ddrphy_addr_remap(pr_to32)) & 0x0000ffff) << 16); 145 if (tmp32 != readl(pr_from32)) { 146 debug("%lx %lx\n", pr_from32, pr_to32); 147 error++; 148 } 149 pr_from32 += 4; 150 pr_to32 += 1; 151 i += 4; 152 } 153 154 if (error) 155 printf("check ddr_pmu_train_dmem code fail=%d", error); 156 else 157 debug("check ddr_pmu_train_dmem code pass\n"); 158} 159 160void ddrphy_trained_csr_save(struct dram_cfg_param *ddrphy_csr, 161 unsigned int num) 162{ 163 int i = 0; 164 165 /* enable the ddrphy apb */ 166 dwc_ddrphy_apb_wr(0xd0000, 0x0); 167 dwc_ddrphy_apb_wr(0xc0080, 0x3); 168 for (i = 0; i < num; i++) { 169 ddrphy_csr->val = dwc_ddrphy_apb_rd(ddrphy_csr->reg); 170 ddrphy_csr++; 171 } 172 /* disable the ddrphy apb */ 173 dwc_ddrphy_apb_wr(0xc0080, 0x2); 174 dwc_ddrphy_apb_wr(0xd0000, 0x1); 175} 176 177void *dram_config_save(struct dram_timing_info *timing_info, unsigned long saved_timing_base) 178{ 179 int i = 0; 180 struct dram_timing_info *saved_timing = (struct dram_timing_info *)saved_timing_base; 181 struct dram_cfg_param *cfg; 182 183 saved_timing->ddrc_cfg_num = timing_info->ddrc_cfg_num; 184 saved_timing->ddrphy_cfg_num = timing_info->ddrphy_cfg_num; 185 saved_timing->ddrphy_trained_csr_num = ddrphy_trained_csr_num; 186 saved_timing->ddrphy_pie_num = timing_info->ddrphy_pie_num; 187 188 /* save the fsp table */ 189 for (i = 0; i < 4; i++) 190 saved_timing->fsp_table[i] = timing_info->fsp_table[i]; 191 192 cfg = (struct dram_cfg_param *)(saved_timing_base + 193 sizeof(*timing_info)); 194 195 /* save ddrc config */ 196 saved_timing->ddrc_cfg = cfg; 197 for (i = 0; i < timing_info->ddrc_cfg_num; i++) { 198 cfg->reg = timing_info->ddrc_cfg[i].reg; 199 cfg->val = timing_info->ddrc_cfg[i].val; 200 cfg++; 201 } 202 203 /* save ddrphy config */ 204 saved_timing->ddrphy_cfg = cfg; 205 for (i = 0; i < timing_info->ddrphy_cfg_num; i++) { 206 cfg->reg = timing_info->ddrphy_cfg[i].reg; 207 cfg->val = timing_info->ddrphy_cfg[i].val; 208 cfg++; 209 } 210 211 /* save the ddrphy csr */ 212 saved_timing->ddrphy_trained_csr = cfg; 213 for (i = 0; i < ddrphy_trained_csr_num; i++) { 214 cfg->reg = ddrphy_trained_csr[i].reg; 215 cfg->val = ddrphy_trained_csr[i].val; 216 cfg++; 217 } 218 219 /* save the ddrphy pie */ 220 saved_timing->ddrphy_pie = cfg; 221 for (i = 0; i < timing_info->ddrphy_pie_num; i++) { 222 cfg->reg = timing_info->ddrphy_pie[i].reg; 223 cfg->val = timing_info->ddrphy_pie[i].val; 224 cfg++; 225 } 226 227 return (void *)cfg; 228} 229