1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2018 NXP
4 */
5
6#include <common.h>
7#include <hang.h>
8#include <init.h>
9#include <log.h>
10#include <asm/arch/clock.h>
11#include <asm/arch/ddr.h>
12#include <asm/arch/imx8mq_pins.h>
13#include <asm/arch/sys_proto.h>
14#include <asm/global_data.h>
15#include <asm/io.h>
16#include <asm/mach-imx/gpio.h>
17#include <asm/mach-imx/iomux-v3.h>
18#include <asm/mach-imx/mxc_i2c.h>
19#include <asm/sections.h>
20#include <linux/delay.h>
21#include <errno.h>
22#include <fsl_esdhc_imx.h>
23#include <mmc.h>
24#include <spl.h>
25
26#include "lpddr4_timing.h"
27
28DECLARE_GLOBAL_DATA_PTR;
29
30#define DDR_DET_1		IMX_GPIO_NR(3, 11)
31#define DDR_DET_2		IMX_GPIO_NR(3, 12)
32#define DDR_DET_3		IMX_GPIO_NR(3, 13)
33
34static iomux_v3_cfg_t const verdet_pads[] = {
35	IMX8MQ_PAD_NAND_DATA01__GPIO3_IO7 | MUX_PAD_CTRL(NO_PAD_CTRL),
36	IMX8MQ_PAD_NAND_DATA02__GPIO3_IO8 | MUX_PAD_CTRL(NO_PAD_CTRL),
37	IMX8MQ_PAD_NAND_DATA03__GPIO3_IO9 | MUX_PAD_CTRL(NO_PAD_CTRL),
38	IMX8MQ_PAD_NAND_DATA04__GPIO3_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
39	IMX8MQ_PAD_NAND_DATA05__GPIO3_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
40	IMX8MQ_PAD_NAND_DATA06__GPIO3_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
41	IMX8MQ_PAD_NAND_DATA07__GPIO3_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL),
42};
43
44/*
45 * DDR_DET_1    DDR_DET_2   DDR_DET_3
46 *    0            0            1       4G LPDDR4
47 *    1            1            1       3G LPDDR4
48 *    1            1            0       2G LPDDR4
49 *    1            0            1       1G LPDDR4
50 */
51static void spl_dram_init(void)
52{
53	struct dram_timing_info *dram_timing;
54	u8 ddr = 0, size;
55
56	imx_iomux_v3_setup_multiple_pads(verdet_pads, ARRAY_SIZE(verdet_pads));
57
58	gpio_request(DDR_DET_1, "ddr_det_1");
59	gpio_direction_input(DDR_DET_1);
60	gpio_request(DDR_DET_2, "ddr_det_2");
61	gpio_direction_input(DDR_DET_2);
62	gpio_request(DDR_DET_3, "ddr_det_3");
63	gpio_direction_input(DDR_DET_3);
64
65	ddr |= !!gpio_get_value(DDR_DET_3) << 0;
66	ddr |= !!gpio_get_value(DDR_DET_2) << 1;
67	ddr |= !!gpio_get_value(DDR_DET_1) << 2;
68
69	switch (ddr) {
70	case 0x1:
71		size = 4;
72		dram_timing = &dram_timing_4gb;
73		break;
74	case 0x7:
75		size = 3;
76		dram_timing = &dram_timing_3gb;
77		break;
78	case 0x6:
79		size = 2;
80		dram_timing = &dram_timing_2gb;
81		break;
82	case 0x5:
83		size = 1;
84		dram_timing = &dram_timing_1gb;
85		break;
86	default:
87		puts("Unknown DDR type!!!\n");
88		return;
89	}
90
91	printf("%s: LPDDR4 %d GiB\n", __func__, size);
92	ddr_init(dram_timing);
93	writel(size, MCU_BOOTROM_BASE_ADDR);
94}
95
96#define USDHC2_CD_GPIO	IMX_GPIO_NR(2, 12)
97#define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10)
98#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19)
99
100int board_mmc_getcd(struct mmc *mmc)
101{
102	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
103	int ret = 0;
104
105	switch (cfg->esdhc_base) {
106	case USDHC1_BASE_ADDR:
107		ret = 1;
108		break;
109	case USDHC2_BASE_ADDR:
110		ret = !gpio_get_value(USDHC2_CD_GPIO);
111		return ret;
112	}
113
114	return 1;
115}
116
117#define USDHC_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \
118			 PAD_CTL_FSEL2)
119#define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1)
120
121static iomux_v3_cfg_t const usdhc1_pads[] = {
122	IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
123	IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
124	IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
125	IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
126	IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
127	IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
128	IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
129	IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
130	IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
131	IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
132	IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
133};
134
135static iomux_v3_cfg_t const usdhc2_pads[] = {
136	IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
137	IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
138	IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
139	IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
140	IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
141	IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
142	IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
143	IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
144};
145
146static struct fsl_esdhc_cfg usdhc_cfg[2] = {
147	{USDHC1_BASE_ADDR, 0, 8},
148	{USDHC2_BASE_ADDR, 0, 4},
149};
150
151int board_mmc_init(struct bd_info *bis)
152{
153	int ret;
154	/*
155	 * According to the board_mmc_init() the following map is done:
156	 * (U-Boot device node)    (Physical Port)
157	 * mmc0                    USDHC1
158	 * mmc1                    USDHC2
159	 */
160	init_clk_usdhc(0);
161	usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT);
162	imx_iomux_v3_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
163	gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset");
164	gpio_direction_output(USDHC1_PWR_GPIO, 0);
165	udelay(500);
166	gpio_direction_output(USDHC1_PWR_GPIO, 1);
167	ret = fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
168	if (ret)
169		return ret;
170
171	init_clk_usdhc(1);
172	usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT);
173	imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
174	gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset");
175	gpio_direction_output(USDHC2_PWR_GPIO, 0);
176	udelay(500);
177	gpio_direction_output(USDHC2_PWR_GPIO, 1);
178	return fsl_esdhc_initialize(bis, &usdhc_cfg[1]);
179}
180
181void spl_board_init(void)
182{
183	puts("Normal Boot\n");
184}
185
186#ifdef CONFIG_SPL_LOAD_FIT
187int board_fit_config_name_match(const char *name)
188{
189	/* Just empty function now - can't decide what to choose */
190	debug("%s: %s\n", __func__, name);
191
192	return 0;
193}
194#endif
195
196void board_init_f(ulong dummy)
197{
198	int ret;
199
200	/* Clear global data */
201	memset((void *)gd, 0, sizeof(gd_t));
202
203	arch_cpu_init();
204
205	init_uart_clk(0);
206
207	board_early_init_f();
208
209	timer_init();
210
211	preloader_console_init();
212
213	/* Clear the BSS. */
214	memset(__bss_start, 0, __bss_end - __bss_start);
215
216	ret = spl_init();
217	if (ret) {
218		debug("spl_init() failed: %d\n", ret);
219		hang();
220	}
221
222	enable_tzc380();
223
224	/* DDR initialization */
225	spl_dram_init();
226
227	board_init_r(NULL, 0);
228}
229