1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2019 NXP
4 *
5 * Generated code from MX8M_DDR_tool
6 * Align with uboot version:
7 * imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.0.0_ga
8 */
9
10#include <linux/kernel.h>
11#include <asm/arch/ddr.h>
12
13static struct dram_cfg_param ddr_ddrc_cfg[] = {
14	/** Initialize DDRC registers **/
15	{ 0x3d400000, 0x81040010 },
16	{ 0x3d400030, 0x20 },
17	{ 0x3d400034, 0x221306 },
18	{ 0x3d400050, 0x210070 },
19	{ 0x3d400054, 0x10008 },
20	{ 0x3d400060, 0x0 },
21	{ 0x3d400064, 0x9200d2 },
22	{ 0x3d4000c0, 0x0 },
23	{ 0x3d4000c4, 0x1000 },
24	{ 0x3d4000d0, 0xc0030126 },
25	{ 0x3d4000d4, 0x770000 },
26	{ 0x3d4000dc, 0x8340105 },
27	{ 0x3d4000e0, 0x180200 },
28	{ 0x3d4000e4, 0x110000 },
29	{ 0x3d4000e8, 0x2000600 },
30	{ 0x3d4000ec, 0x810 },
31	{ 0x3d4000f0, 0x20 },
32	{ 0x3d4000f4, 0xec7 },
33	{ 0x3d400100, 0x11122914 },
34	{ 0x3d400104, 0x4051c },
35	{ 0x3d400108, 0x608050d },
36	{ 0x3d40010c, 0x400c },
37	{ 0x3d400110, 0x8030409 },
38	{ 0x3d400114, 0x6060403 },
39	{ 0x3d40011c, 0x606 },
40	{ 0x3d400120, 0x5050d08 },
41	{ 0x3d400124, 0x2040a },
42	{ 0x3d40012c, 0x1409010e },
43	{ 0x3d400130, 0x8 },
44	{ 0x3d40013c, 0x0 },
45	{ 0x3d400180, 0x1000040 },
46	{ 0x3d400184, 0x493e },
47	{ 0x3d400190, 0x38b8207 },
48	{ 0x3d400194, 0x2020303 },
49	{ 0x3d400198, 0x7f04011 },
50	{ 0x3d40019c, 0xb0 },
51	{ 0x3d4001a0, 0xe0400018 },
52	{ 0x3d4001a4, 0x48005a },
53	{ 0x3d4001a8, 0x80000000 },
54	{ 0x3d4001b0, 0x1 },
55	{ 0x3d4001b4, 0xb07 },
56	{ 0x3d4001b8, 0x4 },
57	{ 0x3d4001c0, 0x1 },
58	{ 0x3d4001c4, 0x0 },
59	{ 0x3d400200, 0x3f1f },
60	{ 0x3d400204, 0x3f0909 },
61	{ 0x3d400208, 0x700 },
62	{ 0x3d40020c, 0x0 },
63	{ 0x3d400210, 0x1f1f },
64	{ 0x3d400214, 0x7070707 },
65	{ 0x3d400218, 0x7070707 },
66	{ 0x3d40021c, 0xf0f },
67	{ 0x3d400220, 0x3f01 },
68	{ 0x3d400240, 0x6000610 },
69	{ 0x3d400244, 0x1323 },
70	{ 0x3d400400, 0x100 },
71	{ 0x3d400250, 0x317d1a07 },
72	{ 0x3d400254, 0xf },
73	{ 0x3d40025c, 0x2a001b76 },
74	{ 0x3d400264, 0x7300b473 },
75	{ 0x3d40026c, 0x30000e06 },
76	{ 0x3d400300, 0x14 },
77	{ 0x3d40036c, 0x10 },
78	{ 0x3d400404, 0x13193 },
79	{ 0x3d400408, 0x6096 },
80	{ 0x3d400490, 0x1 },
81	{ 0x3d400494, 0x2000c00 },
82	{ 0x3d400498, 0x3c00db },
83	{ 0x3d40049c, 0x100009 },
84	{ 0x3d4004a0, 0x2 },
85	{ 0x3d402050, 0x210070 },
86	{ 0x3d402064, 0x40005e },
87	{ 0x3d4020dc, 0x40105 },
88	{ 0x3d4020e0, 0x0 },
89	{ 0x3d4020e8, 0x2000600 },
90	{ 0x3d4020ec, 0x10 },
91	{ 0x3d402100, 0xb081209 },
92	{ 0x3d402104, 0x2020d },
93	{ 0x3d402108, 0x5050309 },
94	{ 0x3d40210c, 0x400c },
95	{ 0x3d402110, 0x5030206 },
96	{ 0x3d402114, 0x3030202 },
97	{ 0x3d40211c, 0x303 },
98	{ 0x3d402120, 0x3030d04 },
99	{ 0x3d402124, 0x20208 },
100	{ 0x3d40212c, 0x1005010e },
101	{ 0x3d402130, 0x8 },
102	{ 0x3d40213c, 0x0 },
103	{ 0x3d402180, 0x1000040 },
104	{ 0x3d402190, 0x3858204 },
105	{ 0x3d402194, 0x2020303 },
106	{ 0x3d4021b4, 0x504 },
107	{ 0x3d4021b8, 0x4 },
108	{ 0x3d402240, 0x6000604 },
109	{ 0x3d4020f4, 0xec7 },
110};
111
112/* PHY Initialize Configuration */
113static struct dram_cfg_param ddr_ddrphy_cfg[] = {
114	{ 0x1005f, 0x2fd },
115	{ 0x1015f, 0x2fd },
116	{ 0x1105f, 0x2fd },
117	{ 0x1115f, 0x2fd },
118	{ 0x11005f, 0x2fd },
119	{ 0x11015f, 0x2fd },
120	{ 0x11105f, 0x2fd },
121	{ 0x11115f, 0x2fd },
122	{ 0x55, 0x355 },
123	{ 0x1055, 0x355 },
124	{ 0x2055, 0x355 },
125	{ 0x3055, 0x355 },
126	{ 0x4055, 0x55 },
127	{ 0x5055, 0x55 },
128	{ 0x6055, 0x355 },
129	{ 0x7055, 0x355 },
130	{ 0x8055, 0x355 },
131	{ 0x9055, 0x355 },
132	{ 0x200c5, 0xa },
133	{ 0x1200c5, 0x6 },
134	{ 0x2002e, 0x2 },
135	{ 0x12002e, 0x1 },
136	{ 0x20024, 0x8 },
137	{ 0x2003a, 0x2 },
138	{ 0x120024, 0x8 },
139	{ 0x2003a, 0x2 },
140	{ 0x20056, 0x6 },
141	{ 0x120056, 0xa },
142	{ 0x1004d, 0x1a },
143	{ 0x1014d, 0x1a },
144	{ 0x1104d, 0x1a },
145	{ 0x1114d, 0x1a },
146	{ 0x11004d, 0x1a },
147	{ 0x11014d, 0x1a },
148	{ 0x11104d, 0x1a },
149	{ 0x11114d, 0x1a },
150	{ 0x10049, 0xe38 },
151	{ 0x10149, 0xe38 },
152	{ 0x11049, 0xe38 },
153	{ 0x11149, 0xe38 },
154	{ 0x110049, 0xe38 },
155	{ 0x110149, 0xe38 },
156	{ 0x111049, 0xe38 },
157	{ 0x111149, 0xe38 },
158	{ 0x43, 0x63 },
159	{ 0x1043, 0x63 },
160	{ 0x2043, 0x63 },
161	{ 0x3043, 0x63 },
162	{ 0x4043, 0x63 },
163	{ 0x5043, 0x63 },
164	{ 0x6043, 0x63 },
165	{ 0x7043, 0x63 },
166	{ 0x8043, 0x63 },
167	{ 0x9043, 0x63 },
168	{ 0x20018, 0x1 },
169	{ 0x20075, 0x2 },
170	{ 0x20050, 0x0 },
171	{ 0x20008, 0x258 },
172	{ 0x120008, 0x10a },
173	{ 0x20088, 0x9 },
174	{ 0x200b2, 0x268 },
175	{ 0x10043, 0x5b1 },
176	{ 0x10143, 0x5b1 },
177	{ 0x11043, 0x5b1 },
178	{ 0x11143, 0x5b1 },
179	{ 0x1200b2, 0x268 },
180	{ 0x110043, 0x5b1 },
181	{ 0x110143, 0x5b1 },
182	{ 0x111043, 0x5b1 },
183	{ 0x111143, 0x5b1 },
184	{ 0x200fa, 0x1 },
185	{ 0x1200fa, 0x1 },
186	{ 0x20019, 0x5 },
187	{ 0x120019, 0x5 },
188	{ 0x200f0, 0x5555 },
189	{ 0x200f1, 0x5555 },
190	{ 0x200f2, 0x5555 },
191	{ 0x200f3, 0x5555 },
192	{ 0x200f4, 0x5555 },
193	{ 0x200f5, 0x5555 },
194	{ 0x200f6, 0x5555 },
195	{ 0x200f7, 0xf000 },
196	{ 0x20025, 0x0 },
197	{ 0x2002d, 0x0 },
198	{ 0x12002d, 0x0 },
199	{ 0x2005b, 0x7529 },
200	{ 0x2005c, 0x0 },
201	{ 0x200c7, 0x21 },
202	{ 0x200ca, 0x24 },
203	{ 0x200cc, 0x1f7 },
204	{ 0x1200c7, 0x21 },
205	{ 0x1200ca, 0x24 },
206	{ 0x1200cc, 0x1f7 },
207	{ 0x2007d, 0x212 },
208	{ 0x12007d, 0x212 },
209	{ 0x2007c, 0x61 },
210	{ 0x12007c, 0x61 },
211	{ 0x1004a, 0x500 },
212	{ 0x1104a, 0x500 },
213	{ 0x2002c, 0x0 },
214};
215
216/* P0 message block parameter for training firmware */
217static struct dram_cfg_param ddr_fsp0_cfg[] = {
218	{ 0xd0000, 0x0 },
219	{ 0x54003, 0x960 },
220	{ 0x54004, 0x2 },
221	{ 0x54005, 0x2830 },
222	{ 0x54006, 0x25e },
223	{ 0x54007, 0x1000 },
224	{ 0x54008, 0x101 },
225	{ 0x5400b, 0x31f },
226	{ 0x5400c, 0xc8 },
227	{ 0x5400d, 0x100 },
228	{ 0x54012, 0x1 },
229	{ 0x5402f, 0x834 },
230	{ 0x54030, 0x105 },
231	{ 0x54031, 0x18 },
232	{ 0x54032, 0x200 },
233	{ 0x54033, 0x200 },
234	{ 0x54034, 0x600 },
235	{ 0x54035, 0x810 },
236	{ 0x54036, 0x101 },
237	{ 0x5403f, 0x1221 },
238	{ 0x541fc, 0x100 },
239	{ 0xd0000, 0x1 },
240};
241
242/* P1 message block parameter for training firmware */
243static struct dram_cfg_param ddr_fsp1_cfg[] = {
244	{ 0xd0000, 0x0 },
245	{ 0x54002, 0x1 },
246	{ 0x54003, 0x42a },
247	{ 0x54004, 0x2 },
248	{ 0x54005, 0x2830 },
249	{ 0x54006, 0x25e },
250	{ 0x54007, 0x1000 },
251	{ 0x54008, 0x101 },
252	{ 0x5400b, 0x21f },
253	{ 0x5400c, 0xc8 },
254	{ 0x5400d, 0x100 },
255	{ 0x54012, 0x1 },
256	{ 0x5402f, 0x4 },
257	{ 0x54030, 0x105 },
258	{ 0x54033, 0x200 },
259	{ 0x54034, 0x600 },
260	{ 0x54035, 0x10 },
261	{ 0x54036, 0x101 },
262	{ 0x5403f, 0x1221 },
263	{ 0x541fc, 0x100 },
264	{ 0xd0000, 0x1 },
265};
266
267/* P0 2D message block parameter for training firmware */
268static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
269	{ 0xd0000, 0x0 },
270	{ 0x54003, 0x960 },
271	{ 0x54004, 0x2 },
272	{ 0x54005, 0x2830 },
273	{ 0x54006, 0x25e },
274	{ 0x54007, 0x1000 },
275	{ 0x54008, 0x101 },
276	{ 0x5400b, 0x61 },
277	{ 0x5400c, 0xc8 },
278	{ 0x5400d, 0x100 },
279	{ 0x5400e, 0x1f7f },
280	{ 0x54012, 0x1 },
281	{ 0x5402f, 0x834 },
282	{ 0x54030, 0x105 },
283	{ 0x54031, 0x18 },
284	{ 0x54032, 0x200 },
285	{ 0x54033, 0x200 },
286	{ 0x54034, 0x600 },
287	{ 0x54035, 0x810 },
288	{ 0x54036, 0x101 },
289	{ 0x5403f, 0x1221 },
290	{ 0x541fc, 0x100 },
291	{ 0xd0000, 0x1 },
292};
293
294/* DRAM PHY init engine image */
295static struct dram_cfg_param ddr_phy_pie[] = {
296	{ 0xd0000, 0x0 },
297	{ 0x90000, 0x10 },
298	{ 0x90001, 0x400 },
299	{ 0x90002, 0x10e },
300	{ 0x90003, 0x0 },
301	{ 0x90004, 0x0 },
302	{ 0x90005, 0x8 },
303	{ 0x90029, 0xb },
304	{ 0x9002a, 0x480 },
305	{ 0x9002b, 0x109 },
306	{ 0x9002c, 0x8 },
307	{ 0x9002d, 0x448 },
308	{ 0x9002e, 0x139 },
309	{ 0x9002f, 0x8 },
310	{ 0x90030, 0x478 },
311	{ 0x90031, 0x109 },
312	{ 0x90032, 0x2 },
313	{ 0x90033, 0x10 },
314	{ 0x90034, 0x139 },
315	{ 0x90035, 0xb },
316	{ 0x90036, 0x7c0 },
317	{ 0x90037, 0x139 },
318	{ 0x90038, 0x44 },
319	{ 0x90039, 0x633 },
320	{ 0x9003a, 0x159 },
321	{ 0x9003b, 0x14f },
322	{ 0x9003c, 0x630 },
323	{ 0x9003d, 0x159 },
324	{ 0x9003e, 0x47 },
325	{ 0x9003f, 0x633 },
326	{ 0x90040, 0x149 },
327	{ 0x90041, 0x4f },
328	{ 0x90042, 0x633 },
329	{ 0x90043, 0x179 },
330	{ 0x90044, 0x8 },
331	{ 0x90045, 0xe0 },
332	{ 0x90046, 0x109 },
333	{ 0x90047, 0x0 },
334	{ 0x90048, 0x7c8 },
335	{ 0x90049, 0x109 },
336	{ 0x9004a, 0x0 },
337	{ 0x9004b, 0x1 },
338	{ 0x9004c, 0x8 },
339	{ 0x9004d, 0x0 },
340	{ 0x9004e, 0x45a },
341	{ 0x9004f, 0x9 },
342	{ 0x90050, 0x0 },
343	{ 0x90051, 0x448 },
344	{ 0x90052, 0x109 },
345	{ 0x90053, 0x40 },
346	{ 0x90054, 0x633 },
347	{ 0x90055, 0x179 },
348	{ 0x90056, 0x1 },
349	{ 0x90057, 0x618 },
350	{ 0x90058, 0x109 },
351	{ 0x90059, 0x40c0 },
352	{ 0x9005a, 0x633 },
353	{ 0x9005b, 0x149 },
354	{ 0x9005c, 0x8 },
355	{ 0x9005d, 0x4 },
356	{ 0x9005e, 0x48 },
357	{ 0x9005f, 0x4040 },
358	{ 0x90060, 0x633 },
359	{ 0x90061, 0x149 },
360	{ 0x90062, 0x0 },
361	{ 0x90063, 0x4 },
362	{ 0x90064, 0x48 },
363	{ 0x90065, 0x40 },
364	{ 0x90066, 0x633 },
365	{ 0x90067, 0x149 },
366	{ 0x90068, 0x10 },
367	{ 0x90069, 0x4 },
368	{ 0x9006a, 0x18 },
369	{ 0x9006b, 0x0 },
370	{ 0x9006c, 0x4 },
371	{ 0x9006d, 0x78 },
372	{ 0x9006e, 0x549 },
373	{ 0x9006f, 0x633 },
374	{ 0x90070, 0x159 },
375	{ 0x90071, 0xd49 },
376	{ 0x90072, 0x633 },
377	{ 0x90073, 0x159 },
378	{ 0x90074, 0x94a },
379	{ 0x90075, 0x633 },
380	{ 0x90076, 0x159 },
381	{ 0x90077, 0x441 },
382	{ 0x90078, 0x633 },
383	{ 0x90079, 0x149 },
384	{ 0x9007a, 0x42 },
385	{ 0x9007b, 0x633 },
386	{ 0x9007c, 0x149 },
387	{ 0x9007d, 0x1 },
388	{ 0x9007e, 0x633 },
389	{ 0x9007f, 0x149 },
390	{ 0x90080, 0x0 },
391	{ 0x90081, 0xe0 },
392	{ 0x90082, 0x109 },
393	{ 0x90083, 0xa },
394	{ 0x90084, 0x10 },
395	{ 0x90085, 0x109 },
396	{ 0x90086, 0x9 },
397	{ 0x90087, 0x3c0 },
398	{ 0x90088, 0x149 },
399	{ 0x90089, 0x9 },
400	{ 0x9008a, 0x3c0 },
401	{ 0x9008b, 0x159 },
402	{ 0x9008c, 0x18 },
403	{ 0x9008d, 0x10 },
404	{ 0x9008e, 0x109 },
405	{ 0x9008f, 0x0 },
406	{ 0x90090, 0x3c0 },
407	{ 0x90091, 0x109 },
408	{ 0x90092, 0x18 },
409	{ 0x90093, 0x4 },
410	{ 0x90094, 0x48 },
411	{ 0x90095, 0x18 },
412	{ 0x90096, 0x4 },
413	{ 0x90097, 0x58 },
414	{ 0x90098, 0xb },
415	{ 0x90099, 0x10 },
416	{ 0x9009a, 0x109 },
417	{ 0x9009b, 0x1 },
418	{ 0x9009c, 0x10 },
419	{ 0x9009d, 0x109 },
420	{ 0x9009e, 0x5 },
421	{ 0x9009f, 0x7c0 },
422	{ 0x900a0, 0x109 },
423	{ 0x900a1, 0x0 },
424	{ 0x900a2, 0x8140 },
425	{ 0x900a3, 0x10c },
426	{ 0x900a4, 0x10 },
427	{ 0x900a5, 0x8138 },
428	{ 0x900a6, 0x10c },
429	{ 0x900a7, 0x8 },
430	{ 0x900a8, 0x7c8 },
431	{ 0x900a9, 0x101 },
432	{ 0x900aa, 0x8 },
433	{ 0x900ab, 0x448 },
434	{ 0x900ac, 0x109 },
435	{ 0x900ad, 0xf },
436	{ 0x900ae, 0x7c0 },
437	{ 0x900af, 0x109 },
438	{ 0x900b0, 0x47 },
439	{ 0x900b1, 0x630 },
440	{ 0x900b2, 0x109 },
441	{ 0x900b3, 0x8 },
442	{ 0x900b4, 0x618 },
443	{ 0x900b5, 0x109 },
444	{ 0x900b6, 0x8 },
445	{ 0x900b7, 0xe0 },
446	{ 0x900b8, 0x109 },
447	{ 0x900b9, 0x0 },
448	{ 0x900ba, 0x7c8 },
449	{ 0x900bb, 0x109 },
450	{ 0x900bc, 0x8 },
451	{ 0x900bd, 0x8140 },
452	{ 0x900be, 0x10c },
453	{ 0x900bf, 0x0 },
454	{ 0x900c0, 0x1 },
455	{ 0x900c1, 0x8 },
456	{ 0x900c2, 0x8 },
457	{ 0x900c3, 0x4 },
458	{ 0x900c4, 0x8 },
459	{ 0x900c5, 0x8 },
460	{ 0x900c6, 0x7c8 },
461	{ 0x900c7, 0x101 },
462	{ 0x90006, 0x0 },
463	{ 0x90007, 0x0 },
464	{ 0x90008, 0x8 },
465	{ 0x90009, 0x0 },
466	{ 0x9000a, 0x0 },
467	{ 0x9000b, 0x0 },
468	{ 0xd00e7, 0x400 },
469	{ 0x90017, 0x0 },
470	{ 0x90026, 0x2b },
471	{ 0x2000b, 0x4b },
472	{ 0x2000c, 0x96 },
473	{ 0x2000d, 0x5dc },
474	{ 0x2000e, 0x2c },
475	{ 0x12000b, 0x21 },
476	{ 0x12000c, 0x42 },
477	{ 0x12000d, 0x29a },
478	{ 0x12000e, 0x21 },
479	{ 0x9000c, 0x0 },
480	{ 0x9000d, 0x173 },
481	{ 0x9000e, 0x60 },
482	{ 0x9000f, 0x6110 },
483	{ 0x90010, 0x2152 },
484	{ 0x90011, 0xdfbd },
485	{ 0x90012, 0xffff },
486	{ 0x90013, 0x6152 },
487	{ 0x20089, 0x1 },
488	{ 0x20088, 0x19 },
489	{ 0xc0080, 0x0 },
490	{ 0xd0000, 0x1 },
491};
492
493static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
494	{
495		/* P0 2400mts 1D */
496		.drate = 2400,
497		.fw_type = FW_1D_IMAGE,
498		.fsp_cfg = ddr_fsp0_cfg,
499		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
500	},
501	{
502		/* P1 1066mts 1D */
503		.drate = 1066,
504		.fw_type = FW_1D_IMAGE,
505		.fsp_cfg = ddr_fsp1_cfg,
506		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
507	},
508	{
509		/* P0 2400mts 2D */
510		.drate = 2400,
511		.fw_type = FW_2D_IMAGE,
512		.fsp_cfg = ddr_fsp0_2d_cfg,
513		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
514	},
515};
516
517/* ddr timing config params */
518struct dram_timing_info dram_timing = {
519	.ddrc_cfg = ddr_ddrc_cfg,
520	.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
521	.ddrphy_cfg = ddr_ddrphy_cfg,
522	.ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
523	.fsp_msg = ddr_dram_fsp_msg,
524	.fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
525	.ddrphy_pie = ddr_phy_pie,
526	.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
527	.fsp_table = { 2400, 1066, },
528};
529