1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright 2022 Marek Vasut <marex@denx.de> 4 */ 5 6#include <common.h> 7#include <hang.h> 8#include <image.h> 9#include <init.h> 10#include <spl.h> 11 12#include <asm-generic/gpio.h> 13#include <asm/arch/clock.h> 14#include <asm/arch/ddr.h> 15#include <asm/arch/imx8mp_pins.h> 16#include <asm/arch/sys_proto.h> 17#include <asm/io.h> 18#include <asm/mach-imx/boot_mode.h> 19 20#include <dm/uclass.h> 21#include <dm/device.h> 22#include <dm/uclass-internal.h> 23#include <dm/device-internal.h> 24 25#include <power/pmic.h> 26#include <power/pca9450.h> 27 28#include "lpddr4_timing.h" 29 30#include "../common/common.h" 31 32DECLARE_GLOBAL_DATA_PTR; 33 34int data_modul_imx_edm_sbc_board_power_init(void) 35{ 36 struct udevice *dev; 37 int ret; 38 39 ret = pmic_get("pmic@25", &dev); 40 if (ret == -ENODEV) { 41 puts("Failed to get PMIC\n"); 42 return 0; 43 } 44 if (ret != 0) 45 return ret; 46 47 /* BUCKxOUT_DVS0/1 control BUCK123 output. */ 48 pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29); 49 50 /* Increase VDD_SOC to typical value 0.95V before first DRAM access. */ 51 if (IS_ENABLED(CONFIG_IMX8M_VDD_SOC_850MV)) 52 /* Set DVS0 to 0.85V for special case. */ 53 pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x14); 54 else 55 pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x1c); 56 57 /* Set DVS1 to 0.85v for suspend. */ 58 pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x14); 59 60 /* 61 * Enable DVS control through PMIC_STBY_REQ and 62 * set B1_ENMODE=1 (ON by PMIC_ON_REQ=H). 63 */ 64 pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59); 65 66 /* Kernel uses OD/OD frequency for SoC. */ 67 68 /* To avoid timing risk from SoC to ARM, increase VDD_ARM to OD voltage 0.95V */ 69 pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x1c); 70 71 /* DRAM Vdd1 always FPWM */ 72 pmic_reg_write(dev, PCA9450_BUCK5CTRL, 0x0d); 73 /* DRAM Vdd2/Vddq always FPWM */ 74 pmic_reg_write(dev, PCA9450_BUCK6CTRL, 0x0d); 75 76 /* Set LDO4 and CONFIG2 to enable the I2C level translator. */ 77 pmic_reg_write(dev, PCA9450_LDO4CTRL, 0x59); 78 pmic_reg_write(dev, PCA9450_CONFIG2, 0x1); 79 80 return 0; 81} 82 83void spl_board_init(void) 84{ 85 /* 86 * Set GIC clock to 500 MHz for OD VDD_SOC. Kernel driver does not 87 * allow to change it. Should set the clock after PMIC setting done. 88 * Default is 400 MHz (system_pll1_800m with div = 2) set by ROM for 89 * ND VDD_SOC. 90 */ 91 clock_enable(CCGR_GIC, 0); 92 clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(5)); 93 clock_enable(CCGR_GIC, 1); 94} 95 96int spl_board_boot_device(enum boot_device boot_dev_spl) 97{ 98 if (boot_dev_spl == SPI_NOR_BOOT) /* SPI NOR */ 99 return BOOT_DEVICE_SPI; 100 101 if (boot_dev_spl == MMC3_BOOT) /* eMMC */ 102 return BOOT_DEVICE_MMC2; 103 104 return BOOT_DEVICE_MMC1; /* SD */ 105} 106 107void board_boot_order(u32 *spl_boot_list) 108{ 109 int boot_device = spl_boot_device(); 110 111 spl_boot_list[0] = boot_device; /* 1:SD 2:eMMC 8:SPI NOR */ 112 113 if (boot_device == BOOT_DEVICE_SPI) { /* SPI, eMMC, SD */ 114 spl_boot_list[1] = BOOT_DEVICE_MMC2; /* eMMC */ 115 spl_boot_list[2] = BOOT_DEVICE_MMC1; /* SD */ 116 } else if (boot_device == BOOT_DEVICE_MMC1) { /* SD, eMMC, SPI */ 117 spl_boot_list[1] = BOOT_DEVICE_MMC2; /* eMMC */ 118 spl_boot_list[2] = BOOT_DEVICE_SPI; /* SPI */ 119 } else { /* eMMC, SPI, SD */ 120 spl_boot_list[1] = BOOT_DEVICE_SPI; /* SPI */ 121 spl_boot_list[2] = BOOT_DEVICE_MMC1; /* SD */ 122 } 123 124 spl_boot_list[3] = BOOT_DEVICE_UART; /* YModem */ 125 spl_boot_list[4] = BOOT_DEVICE_NONE; 126} 127 128unsigned long board_spl_mmc_get_uboot_raw_sector(struct mmc *mmc, unsigned long sect) 129{ 130 const u32 boot_dev = spl_boot_device(); 131 int part; 132 133 if (boot_dev == BOOT_DEVICE_MMC2) { /* eMMC */ 134 part = spl_mmc_emmc_boot_partition(mmc); 135 if (part == 1 || part == 2) /* eMMC BOOT1/BOOT2 HW partitions */ 136 return sect - 0x40; 137 } 138 139 return sect; 140} 141 142static struct dram_timing_info *dram_timing_info[8] = { 143 &dmo_imx8mp_sbc_dram_timing_32_32, /* 32 Gbit x32 */ 144 NULL, /* 32 Gbit x16 */ 145 NULL, /* 16 Gbit x32 */ 146 NULL, /* 16 Gbit x16 */ 147 NULL, /* 8 Gbit x32 */ 148 NULL, /* 8 Gbit x16 */ 149 NULL, /* INVALID */ 150 NULL, /* INVALID */ 151}; 152 153void board_init_f(ulong dummy) 154{ 155 dmo_board_init_f(MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B, dram_timing_info); 156} 157