Searched refs:c7 (Results 1 - 15 of 15) sorted by relevance

/u-boot/arch/arm/mach-mvebu/
H A Dlowlevel.S23 mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs
24 mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
25 mcr p15, 0, r0, c7, c5, 6 @ invalidate BP array
26 mcr p15, 0, r0, c7, c10, 4 @ DSB
27 mcr p15, 0, r0, c7, c5, 4 @ ISB
H A Dlowlevel_spl.S40 mcr p15, 0, r0, c7, c6, 1
56 mcr p15, 0, r0, c7, c10, 5 /* @ data memory barrier */
57 mcr p15, 0, r0, c7, c14, 1 /* @ clean & invalidate D line */
58 mcr p15, 0, r0, c7, c10, 4 /* @ data sync barrier */
75 mcr p15, 0, r0, c7, c14, 1 /* @ clean & invalidate D line */
/u-boot/arch/arm/cpu/arm1136/
H A Dstart.S71 mcr p15, 0, r0, c7, c7, 0 /* Invalidate I+D+BTB caches */
72 mcr p15, 0, r0, c8, c7, 0 /* Invalidate Unified TLB */
/u-boot/arch/arm/cpu/arm1176/
H A Dstart.S73 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
74 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
/u-boot/arch/arm/cpu/arm920t/
H A Dstart.S73 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
74 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
/u-boot/arch/arm/cpu/arm926ejs/
H A Dstart.S85 mrc p15, 0, r15, c7, c10, 3
88 mcr p15, 0, r0, c8, c7, 0 /* invalidate TLB */
89 mcr p15, 0, r0, c7, c5, 0 /* invalidate I Cache */
/u-boot/arch/arm/mach-imx/mx7/
H A Dpsci-suspend.S43 mcr p15, 0, r5, c7, c6, 2
57 mcr p15, 0, r6, c7, c5, 0
58 mcr p15, 0, r6, c7, c5, 6
/u-boot/arch/arm/cpu/arm946es/
H A Dstart.S79 mcr p15, 0, r0, c7, c5, 0 /* flush v4 I-cache */
80 mcr p15, 0, r0, c7, c6, 0 /* flush v4 D-cache */
/u-boot/arch/arm/lib/
H A Drelocate.S125 mcr p15, 0, r0, c7, c7, 0 /* invalidate icache */
126 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
/u-boot/arch/m68k/include/asm/coldfire/
H A Dskha.h37 u32 c7; /* 0x88 Context 7 */ member in struct:skha_ctrl
/u-boot/arch/arm/cpu/armv7/
H A Dstart.S136 mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
217 mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs
218 mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
219 mcr p15, 0, r0, c7, c5, 6 @ invalidate BP array
H A Dcache_v7_asm.S58 mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way
92 * mcr p15, 0, r11, c7, c14, 2
94 * mcr p15, 0, r11, c7, c6, 2
128 mcr p15, 0, r11, c7, c6, 2 @ invalidate by set/way
H A Dpsci.S200 mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way
/u-boot/arch/arm/mach-omap2/omap3/
H A Dlowlevel_init.S34 mcr p15, 0, r0, c7, c10, 4 @ DSB
35 mcr p15, 0, r0, c7, c10, 5 @ DMB
/u-boot/arch/arm/mach-uniphier/arm32/
H A Dlowlevel_init.S62 mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs

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