/u-boot/arch/arm/mach-mvebu/ |
H A D | lowlevel.S | 23 mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs 24 mcr p15, 0, r0, c7, c5, 0 @ invalidate icache 25 mcr p15, 0, r0, c7, c5, 6 @ invalidate BP array 26 mcr p15, 0, r0, c7, c10, 4 @ DSB 27 mcr p15, 0, r0, c7, c5, 4 @ ISB
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H A D | lowlevel_spl.S | 40 mcr p15, 0, r0, c7, c6, 1 56 mcr p15, 0, r0, c7, c10, 5 /* @ data memory barrier */ 57 mcr p15, 0, r0, c7, c14, 1 /* @ clean & invalidate D line */ 58 mcr p15, 0, r0, c7, c10, 4 /* @ data sync barrier */ 75 mcr p15, 0, r0, c7, c14, 1 /* @ clean & invalidate D line */
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/u-boot/arch/arm/cpu/arm1136/ |
H A D | start.S | 71 mcr p15, 0, r0, c7, c7, 0 /* Invalidate I+D+BTB caches */ 72 mcr p15, 0, r0, c8, c7, 0 /* Invalidate Unified TLB */
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/u-boot/arch/arm/cpu/arm1176/ |
H A D | start.S | 73 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ 74 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
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/u-boot/arch/arm/cpu/arm920t/ |
H A D | start.S | 73 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ 74 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
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/u-boot/arch/arm/cpu/arm926ejs/ |
H A D | start.S | 85 mrc p15, 0, r15, c7, c10, 3 88 mcr p15, 0, r0, c8, c7, 0 /* invalidate TLB */ 89 mcr p15, 0, r0, c7, c5, 0 /* invalidate I Cache */
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/u-boot/arch/arm/mach-imx/mx7/ |
H A D | psci-suspend.S | 43 mcr p15, 0, r5, c7, c6, 2 57 mcr p15, 0, r6, c7, c5, 0 58 mcr p15, 0, r6, c7, c5, 6
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/u-boot/arch/arm/cpu/arm946es/ |
H A D | start.S | 79 mcr p15, 0, r0, c7, c5, 0 /* flush v4 I-cache */ 80 mcr p15, 0, r0, c7, c6, 0 /* flush v4 D-cache */
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/u-boot/arch/arm/lib/ |
H A D | relocate.S | 125 mcr p15, 0, r0, c7, c7, 0 /* invalidate icache */ 126 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
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/u-boot/arch/m68k/include/asm/coldfire/ |
H A D | skha.h | 37 u32 c7; /* 0x88 Context 7 */ member in struct:skha_ctrl
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/u-boot/arch/arm/cpu/armv7/ |
H A D | start.S | 136 mcr p15, 0, r0, c7, c5, 0 @ invalidate icache 217 mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs 218 mcr p15, 0, r0, c7, c5, 0 @ invalidate icache 219 mcr p15, 0, r0, c7, c5, 6 @ invalidate BP array
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H A D | cache_v7_asm.S | 58 mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way 92 * mcr p15, 0, r11, c7, c14, 2 94 * mcr p15, 0, r11, c7, c6, 2 128 mcr p15, 0, r11, c7, c6, 2 @ invalidate by set/way
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H A D | psci.S | 200 mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way
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/u-boot/arch/arm/mach-omap2/omap3/ |
H A D | lowlevel_init.S | 34 mcr p15, 0, r0, c7, c10, 4 @ DSB 35 mcr p15, 0, r0, c7, c10, 5 @ DMB
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/u-boot/arch/arm/mach-uniphier/arm32/ |
H A D | lowlevel_init.S | 62 mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs
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