1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 *  armboot - Startup Code for ARM1176 CPU-core
4 *
5 * Copyright (c) 2007	Samsung Electronics
6 *
7 * Copyright (C) 2008
8 * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
9 *
10 * 2007-09-21 - Restructured codes by jsgood (jsgood.yang@samsung.com)
11 * 2007-09-21 - Added MoviNAND and OneNAND boot codes by
12 * jsgood (jsgood.yang@samsung.com)
13 * Base codes by scsuh (sc.suh)
14 */
15
16#include <asm-offsets.h>
17#include <config.h>
18#include <linux/linkage.h>
19
20/*
21 *************************************************************************
22 *
23 * Startup Code (reset vector)
24 *
25 * do important init only if we don't start from memory!
26 * setup Memory and board specific bits prior to relocation.
27 * relocate armboot to ram
28 * setup stack
29 *
30 *************************************************************************
31 */
32
33	.globl reset
34
35reset:
36	/* Allow the board to save important registers */
37	b	save_boot_params
38.globl	save_boot_params_ret
39save_boot_params_ret:
40
41	/*
42	 * set the cpu to SVC32 mode
43	 */
44	mrs	r0, cpsr
45	bic	r0, r0, #0x3f
46	orr	r0, r0, #0xd3
47	msr	cpsr, r0
48
49/*
50 *************************************************************************
51 *
52 * CPU_init_critical registers
53 *
54 * setup important registers
55 * setup memory timing
56 *
57 *************************************************************************
58 */
59	/*
60	 * we do sys-critical inits only at reboot,
61	 * not when booting from ram!
62	 */
63cpu_init_crit:
64	/*
65	 * When booting from NAND - it has definitely been a reset, so, no need
66	 * to flush caches and disable the MMU
67	 */
68#ifndef CONFIG_SPL_BUILD
69	/*
70	 * flush v4 I/D caches
71	 */
72	mov	r0, #0
73	mcr	p15, 0, r0, c7, c7, 0	/* flush v3/v4 cache */
74	mcr	p15, 0, r0, c8, c7, 0	/* flush v4 TLB */
75
76	/*
77	 * disable MMU stuff and caches
78	 */
79	mrc	p15, 0, r0, c1, c0, 0
80	bic	r0, r0, #0x00002300	@ clear bits 13, 9:8 (--V- --RS)
81	bic	r0, r0, #0x00000087	@ clear bits 7, 2:0 (B--- -CAM)
82	orr	r0, r0, #0x00000002	@ set bit 1 (A) Align
83	orr	r0, r0, #0x00001000	@ set bit 12 (I) I-Cache
84
85	/* Prepare to disable the MMU */
86	adr	r2, mmu_disable_phys
87	sub	r2, r2, #(CFG_SYS_UBOOT_BASE - CONFIG_TEXT_BASE)
88	b	mmu_disable
89
90	.align 5
91	/* Run in a single cache-line */
92mmu_disable:
93	mcr	p15, 0, r0, c1, c0, 0
94	nop
95	nop
96	mov	pc, r2
97mmu_disable_phys:
98
99#endif
100
101	/*
102	 * Go setup Memory and board specific bits prior to relocation.
103	 */
104	bl	lowlevel_init		/* go setup pll,mux,memory */
105
106	bl	_main
107
108/*------------------------------------------------------------------------------*/
109
110	.globl	c_runtime_cpu_setup
111c_runtime_cpu_setup:
112
113	mov	pc, lr
114
115WEAK(save_boot_params)
116	b	save_boot_params_ret	/* back to my caller */
117ENDPROC(save_boot_params)
118