1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 *  armboot - Startup Code for OMP2420/ARM1136 CPU-core
4 *
5 *  Copyright (c) 2004	Texas Instruments <r-woodruff2@ti.com>
6 *
7 *  Copyright (c) 2001	Marius Gr��ger <mag@sysgo.de>
8 *  Copyright (c) 2002	Alex Z��pke <azu@sysgo.de>
9 *  Copyright (c) 2002	Gary Jennejohn <garyj@denx.de>
10 *  Copyright (c) 2003	Richard Woodruff <r-woodruff2@ti.com>
11 *  Copyright (c) 2003	Kshitij <kshitij@ti.com>
12 */
13
14#include <asm-offsets.h>
15#include <config.h>
16
17/*
18 *************************************************************************
19 *
20 * Startup Code (reset vector)
21 *
22 * do important init only if we don't start from memory!
23 * setup Memory and board specific bits prior to relocation.
24 * relocate armboot to ram
25 * setup stack
26 *
27 *************************************************************************
28 */
29
30	.globl	reset
31
32reset:
33	/*
34	 * set the cpu to SVC32 mode
35	 */
36	mrs	r0,cpsr
37	bic	r0,r0,#0x1f
38	orr	r0,r0,#0xd3
39	msr	cpsr,r0
40
41	/* the mask ROM code should have PLL and others stable */
42#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
43	bl  cpu_init_crit
44#endif
45
46	bl	_main
47
48/*------------------------------------------------------------------------------*/
49
50	.globl	c_runtime_cpu_setup
51c_runtime_cpu_setup:
52
53	bx	lr
54
55/*
56 *************************************************************************
57 *
58 * CPU_init_critical registers
59 *
60 * setup important registers
61 * setup memory timing
62 *
63 *************************************************************************
64 */
65#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
66cpu_init_crit:
67	/*
68	 * flush v4 I/D caches
69	 */
70	mov	r0, #0
71	mcr	p15, 0, r0, c7, c7, 0	/* Invalidate I+D+BTB caches */
72	mcr	p15, 0, r0, c8, c7, 0	/* Invalidate Unified TLB */
73
74	/*
75	 * disable MMU stuff and caches
76	 */
77	mrc	p15, 0, r0, c1, c0, 0
78	bic	r0, r0, #0x00002300	@ clear bits 13, 9:8 (--V- --RS)
79	bic	r0, r0, #0x00000087	@ clear bits 7, 2:0 (B--- -CAM)
80	orr	r0, r0, #0x00000002	@ set bit 1 (A) Align
81	orr	r0, r0, #0x00001000	@ set bit 12 (I) I-Cache
82	mcr	p15, 0, r0, c1, c0, 0
83
84#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
85	/*
86	 * Jump to board specific initialization... The Mask ROM will have already initialized
87	 * basic memory.  Go here to bump up clock rate and handle wake up conditions.
88	 */
89	mov	ip, lr		/* persevere link reg across call */
90	bl	lowlevel_init	/* go setup pll,mux,memory */
91	mov	lr, ip		/* restore link */
92#endif
93	mov	pc, lr		/* back to my caller */
94#endif /* !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */
95