1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 *  armboot - Startup Code for ARM920 CPU-core
4 *
5 *  Copyright (c) 2001	Marius Gr��ger <mag@sysgo.de>
6 *  Copyright (c) 2002	Alex Z��pke <azu@sysgo.de>
7 *  Copyright (c) 2002	Gary Jennejohn <garyj@denx.de>
8 */
9
10#include <asm-offsets.h>
11#include <common.h>
12#include <config.h>
13
14/*
15 *************************************************************************
16 *
17 * Startup Code (called from the ARM reset exception vector)
18 *
19 * do important init only if we don't start from memory!
20 * relocate armboot to ram
21 * setup stack
22 * jump to second stage
23 *
24 *************************************************************************
25 */
26
27	.globl	reset
28
29reset:
30	/*
31	 * set the cpu to SVC32 mode
32	 */
33	mrs	r0, cpsr
34	bic	r0, r0, #0x1f
35	orr	r0, r0, #0xd3
36	msr	cpsr, r0
37
38	/*
39	 * we do sys-critical inits only at reboot,
40	 * not when booting from ram!
41	 */
42#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
43	bl	cpu_init_crit
44#endif
45
46	bl	_main
47
48/*------------------------------------------------------------------------------*/
49
50	.globl	c_runtime_cpu_setup
51c_runtime_cpu_setup:
52
53	mov	pc, lr
54
55/*
56 *************************************************************************
57 *
58 * CPU_init_critical registers
59 *
60 * setup important registers
61 * setup memory timing
62 *
63 *************************************************************************
64 */
65
66
67#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
68cpu_init_crit:
69	/*
70	 * flush v4 I/D caches
71	 */
72	mov	r0, #0
73	mcr	p15, 0, r0, c7, c7, 0	/* flush v3/v4 cache */
74	mcr	p15, 0, r0, c8, c7, 0	/* flush v4 TLB */
75
76	/*
77	 * disable MMU stuff and caches
78	 */
79	mrc	p15, 0, r0, c1, c0, 0
80	bic	r0, r0, #0x00002300	@ clear bits 13, 9:8 (--V- --RS)
81	bic	r0, r0, #0x00000087	@ clear bits 7, 2:0 (B--- -CAM)
82	orr	r0, r0, #0x00000002	@ set bit 1 (A) Align
83	orr	r0, r0, #0x00001000	@ set bit 12 (I) I-Cache
84	mcr	p15, 0, r0, c1, c0, 0
85
86#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
87	/*
88	 * before relocating, we have to setup RAM timing
89	 * because memory timing is board-dependend, you will
90	 * find a lowlevel_init.S in your board directory.
91	 */
92	mov	ip, lr
93
94	bl	lowlevel_init
95	mov	lr, ip
96#endif
97	mov	pc, lr
98#endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */
99