1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Symmetric Key Hardware Accelerator Memory Map
4 *
5 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7 */
8
9#ifndef __SKHA_H__
10#define __SKHA_H__
11
12typedef struct skha_ctrl {
13	u32 mr;			/* 0x00 Mode */
14	u32 cr;			/* 0x04 Control */
15	u32 cmr;		/* 0x08 Command */
16	u32 sr;			/* 0x0C Status */
17	u32 esr;		/* 0x10 Error Status */
18	u32 emr;		/* 0x14 Error Status Mask Register) */
19	u32 ksr;		/* 0x18 Key Size */
20	u32 dsr;		/* 0x1C Data Size */
21	u32 in;			/* 0x20 Input FIFO */
22	u32 out;		/* 0x24 Output FIFO */
23	u32 res1[2];		/* 0x28 - 0x2F */
24	u32 kdr1;		/* 0x30 Key Data 1  */
25	u32 kdr2;		/* 0x34 Key Data 2 */
26	u32 kdr3;		/* 0x38 Key Data 3 */
27	u32 kdr4;		/* 0x3C Key Data 4 */
28	u32 kdr5;		/* 0x40 Key Data 5 */
29	u32 kdr6;		/* 0x44 Key Data 6 */
30	u32 res2[10];		/* 0x48 - 0x6F */
31	u32 c1;			/* 0x70 Context 1 */
32	u32 c2;			/* 0x74 Context 2 */
33	u32 c3;			/* 0x78 Context 3 */
34	u32 c4;			/* 0x7C Context 4 */
35	u32 c5;			/* 0x80 Context 5 */
36	u32 c6;			/* 0x84 Context 6 */
37	u32 c7;			/* 0x88 Context 7 */
38	u32 c8;			/* 0x8C Context 8 */
39	u32 c9;			/* 0x90 Context 9 */
40	u32 c10;		/* 0x94 Context 10 */
41	u32 c11;		/* 0x98 Context 11 */
42	u32 c12;		/* 0x9C Context 12 - 5235, 5271, 5272 */
43} skha_t;
44
45#ifdef CONFIG_MCF532x
46#define	SKHA_MODE_CTRM(x)	(((x) & 0x0F) << 9)
47#define	SKHA_MODE_CTRM_MASK	(0xFFFFE1FF)
48#define	SKHA_MODE_DKP		(0x00000100)
49#else
50#define	SKHA_MODE_CTRM(x)	(((x) & 0x0F) << 8)
51#define	SKHA_MODE_CTRM_MASK	(0xFFFFF0FF)
52#define	SKHA_MODE_DKP		(0x00000080)
53#endif
54#define	SKHA_MODE_CM(x)		(((x) & 0x03) << 3)
55#define	SKHA_MODE_CM_MASK	(0xFFFFFFE7)
56#define	SKHA_MODE_DIR		(0x00000004)
57#define	SKHA_MODE_ALG(x)	((x) & 0x03)
58#define	SKHA_MODE_ALG_MASK	(0xFFFFFFFC)
59
60#define SHKA_CR_ODMAL(x)	(((x) & 0x3F) << 24)
61#define SHKA_CR_ODMAL_MASK	(0xC0FFFFFF)
62#define SHKA_CR_IDMAL(x)	(((x) & 0x3F) << 16)
63#define SHKA_CR_IDMAL_MASK	(0xFFC0FFFF)
64#define SHKA_CR_END		(0x00000008)
65#define SHKA_CR_ODMA		(0x00000004)
66#define SHKA_CR_IDMA		(0x00000002)
67#define	SKHA_CR_IE		(0x00000001)
68
69#define	SKHA_CMR_GO		(0x00000008)
70#define	SKHA_CMR_CI		(0x00000004)
71#define	SKHA_CMR_RI		(0x00000002)
72#define	SKHA_CMR_SWR		(0x00000001)
73
74#define SKHA_SR_OFL(x)		(((x) & 0xFF) << 24)
75#define SKHA_SR_OFL_MASK	(0x00FFFFFF)
76#define SKHA_SR_IFL(x)		(((x) & 0xFF) << 16)
77#define SKHA_SR_IFL_MASK	(0xFF00FFFF)
78#define SKHA_SR_AESES(x)	(((x) & 0x1F) << 11)
79#define SKHA_SR_AESES_MASK	(0xFFFF07FF)
80#define SKHA_SR_DESES(x)	(((x) & 0x7) << 8)
81#define SKHA_SR_DESES_MASK	(0xFFFFF8FF)
82#define SKHA_SR_BUSY		(0x00000010)
83#define SKHA_SR_RD		(0x00000008)
84#define SKHA_SR_ERR		(0x00000004)
85#define SKHA_SR_DONE		(0x00000002)
86#define SKHA_SR_INT		(0x00000001)
87
88#define SHKA_ESE_DRL		(0x00000800)
89#define	SKHA_ESR_KRE		(0x00000400)
90#define	SKHA_ESR_KPE		(0x00000200)
91#define	SKHA_ESR_ERE		(0x00000100)
92#define	SKHA_ESR_RMDP		(0x00000080)
93#define	SKHA_ESR_KSE		(0x00000040)
94#define	SKHA_ESR_DSE		(0x00000020)
95#define	SKHA_ESR_IME		(0x00000010)
96#define	SKHA_ESR_NEOF		(0x00000008)
97#define	SKHA_ESR_NEIF		(0x00000004)
98#define	SKHA_ESR_OFU		(0x00000002)
99#define	SKHA_ESR_IFO		(0x00000001)
100
101#define	SKHA_KSR_SZ(x)		((x) & 0x3F)
102#define	SKHA_KSR_SZ_MASK	(0xFFFFFFC0)
103
104#endif				/* __SKHA_H__ */
105