1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright (C) 2012-2015 Panasonic Corporation
4 * Copyright (C) 2015-2016 Socionext Inc.
5 *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
6 */
7
8#include <config.h>
9#include <linux/linkage.h>
10#include <linux/sizes.h>
11#include <asm/system.h>
12
13ENTRY(lowlevel_init)
14	mov	r8, lr			@ persevere link reg across call
15
16	/*
17	 * The UniPhier Boot ROM loads SPL code to the L2 cache.
18	 * But CPUs can only do instruction fetch now because start.S has
19	 * cleared C and M bits.
20	 * First we need to turn on MMU and Dcache again to get back
21	 * data access to L2.
22	 */
23	mrc	p15, 0, r0, c1, c0, 0	@ SCTLR (System Control Register)
24	orr	r0, r0, #(CR_C | CR_M)	@ enable MMU and Dcache
25	mcr	p15, 0, r0, c1, c0, 0
26
27#ifdef CONFIG_DEBUG_LL
28	bl	debug_ll_init
29#endif
30
31	bl	setup_init_ram		@ RAM area for stack and page table
32
33	/*
34	 * Now we are using the page table embedded in the Boot ROM.
35	 * What we need to do next is to create a page table and switch
36	 * over to it.
37	 */
38	bl	create_page_table
39	bl	__v7_flush_dcache_all
40
41	/* Disable MMU and Dcache before switching Page Table */
42	mrc	p15, 0, r0, c1, c0, 0	@ SCTLR (System Control Register)
43	bic	r0, r0, #(CR_C | CR_M)	@ disable MMU and Dcache
44	mcr	p15, 0, r0, c1, c0, 0
45
46	bl	enable_mmu
47
48	mov	lr, r8			@ restore link
49	mov	pc, lr			@ back to my caller
50ENDPROC(lowlevel_init)
51
52ENTRY(enable_mmu)
53	mrc	p15, 0, r0, c2, c0, 2	@ TTBCR (Translation Table Base Control Register)
54	bic	r0, r0, #0x37
55	orr	r0, r0, #0x20		@ disable TTBR1
56	mcr	p15, 0, r0, c2, c0, 2
57
58	orr	r0, r12, #0x8		@ Outer Cacheability for table walks: WBWA
59	mcr	p15, 0, r0, c2, c0, 0   @ TTBR0
60
61	mov	r0, #0
62	mcr	p15, 0, r0, c8, c7, 0	@ invalidate TLBs
63
64	mov	r0, #-1			@ manager for all domains (No permission check)
65	mcr	p15, 0, r0, c3, c0, 0   @ DACR (Domain Access Control Register)
66
67	dsb
68	isb
69	/*
70	 * MMU on:
71	 * TLBs was already invalidated in "../start.S"
72	 * So, we don't need to invalidate it here.
73	 */
74	mrc	p15, 0, r0, c1, c0, 0	@ SCTLR (System Control Register)
75	orr	r0, r0, #(CR_C | CR_M)	@ MMU and Dcache enable
76	mcr	p15, 0, r0, c1, c0, 0
77
78	mov	pc, lr
79ENDPROC(enable_mmu)
80
81/*
82 * For PH1-Pro4 or older SoCs, the size of WAY is 32KB.
83 * It is large enough for tmp RAM.
84 */
85#define BOOT_RAM_SIZE	(SZ_32K)
86#define BOOT_RAM_BASE	((CONFIG_SPL_STACK) - (BOOT_RAM_SIZE))
87#define BOOT_RAM_WAYS	(0x00000100)	@ way 8
88
89#define SSCO_BASE		0x506c0000
90#define SSCOPE			0x244
91#define SSCOQM			0x248
92#define SSCOQAD			0x24c
93#define SSCOQSZ			0x250
94#define SSCOQWN			0x258
95#define SSCOPPQSEF		0x25c
96#define SSCOLPQS		0x260
97
98ENTRY(setup_init_ram)
99	ldr	r1, = SSCO_BASE
100
101	/* Touch to zero for the boot way */
1020:	ldr	r0, = 0x00408006	@ touch to zero with address range
103	str	r0, [r1, #SSCOQM]
104	ldr	r0, = BOOT_RAM_BASE
105	str	r0, [r1, #SSCOQAD]
106	ldr	r0, = BOOT_RAM_SIZE
107	str	r0, [r1, #SSCOQSZ]
108	ldr	r0, = BOOT_RAM_WAYS
109	str	r0, [r1, #SSCOQWN]
110	ldr	r0, [r1, #SSCOPPQSEF]
111	cmp	r0, #0			@ check if the command is successfully set
112	bne	0b			@ try again if an error occurs
113
1141:	ldr	r0, [r1, #SSCOLPQS]
115	cmp	r0, #0x4
116	bne	1b			@ wait until the operation is completed
117	str	r0, [r1, #SSCOLPQS]	@ clear the complete notification flag
118
119	mov	pc, lr
120ENDPROC(setup_init_ram)
121
122#define DEVICE	0x00002002 /* Non-shareable Device */
123#define NORMAL	0x0000000e /* Normal Memory Write-Back, No Write-Allocate */
124
125ENTRY(create_page_table)
126	ldr	r0, = DEVICE
127	ldr	r1, = BOOT_RAM_BASE
128	mov	r12, r1			@ r12 is preserved during D-cache flush
1290:	str	r0, [r1], #4		@ specify all the sections as Device
130	adds	r0, r0, #0x00100000
131	bcc	0b
132
133	ldr	r0, = NORMAL
134	str	r0, [r12]		@ mark the first section as Normal
135	add	r0, r0, #0x00100000
136	str	r0, [r12, #4]		@ mark the second section as Normal
137	mov	pc, lr
138ENDPROC(create_page_table)
139