1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Board specific setup info 4 * 5 * (C) Copyright 2008 6 * Texas Instruments, <www.ti.com> 7 * 8 * Initial Code by: 9 * Richard Woodruff <r-woodruff2@ti.com> 10 * Syed Mohammed Khasim <khasim@ti.com> 11 */ 12 13#include <config.h> 14#include <asm/arch/mem.h> 15#include <asm/arch/clocks_omap3.h> 16#include <linux/linkage.h> 17 18.arch_extension sec 19 20/* 21 * Funtion for making PPA HAL API calls in secure devices 22 * Input: 23 * R0 - Service ID 24 * R1 - paramer list 25 */ 26ENTRY(do_omap3_emu_romcode_call) 27 PUSH {r4-r12, lr} @ Save all registers from ROM code! 28 MOV r12, r0 @ Copy the Secure Service ID in R12 29 MOV r3, r1 @ Copy the pointer to va_list in R3 30 MOV r1, #0 @ Process ID - 0 31 MOV r2, #OMAP3_EMU_HAL_START_HAL_CRITICAL @ Copy the pointer 32 @ to va_list in R3 33 MOV r6, #0xFF @ Indicate new Task call 34 mcr p15, 0, r0, c7, c10, 4 @ DSB 35 mcr p15, 0, r0, c7, c10, 5 @ DMB 36 SMC #1 @ Call PPA service 37 POP {r4-r12, pc} 38ENDPROC(do_omap3_emu_romcode_call) 39 40#if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_NAND_BOOT) 41/************************************************************************** 42 * cpy_clk_code: relocates clock code into SRAM where its safer to execute 43 * R1 = SRAM destination address. 44 *************************************************************************/ 45ENTRY(cpy_clk_code) 46 /* Copy DPLL code into SRAM */ 47 adr r0, go_to_speed /* copy from start of go_to_speed... */ 48 adr r2, go_to_speed_end /* ... up to start of go_to_speed_end */ 49next2: 50 ldmia r0!, {r3 - r10} /* copy from source address [r0] */ 51 stmia r1!, {r3 - r10} /* copy to target address [r1] */ 52 cmp r0, r2 /* until source end address [r2] */ 53 blo next2 54 mov pc, lr /* back to caller */ 55ENDPROC(cpy_clk_code) 56 57/* *************************************************************************** 58 * go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed 59 * -executed from SRAM. 60 * R0 = CM_CLKEN_PLL-bypass value 61 * R1 = CM_CLKSEL1_PLL-m, n, and divider values 62 * R2 = CM_CLKSEL_CORE-divider values 63 * R3 = CM_IDLEST_CKGEN - addr dpll lock wait 64 * 65 * Note: If core unlocks/relocks and SDRAM is running fast already it gets 66 * confused. A reset of the controller gets it back. Taking away its 67 * L3 when its not in self refresh seems bad for it. Normally, this 68 * code runs from flash before SDR is init so that should be ok. 69 ****************************************************************************/ 70ENTRY(go_to_speed) 71 stmfd sp!, {r4 - r6} 72 73 /* move into fast relock bypass */ 74 ldr r4, pll_ctl_add 75 str r0, [r4] 76wait1: 77 ldr r5, [r3] /* get status */ 78 and r5, r5, #0x1 /* isolate core status */ 79 cmp r5, #0x1 /* still locked? */ 80 beq wait1 /* if lock, loop */ 81 82 /* set new dpll dividers _after_ in bypass */ 83 ldr r5, pll_div_add1 84 str r1, [r5] /* set m, n, m2 */ 85 ldr r5, pll_div_add2 86 str r2, [r5] /* set l3/l4/.. dividers*/ 87 ldr r5, pll_div_add3 /* wkup */ 88 ldr r2, pll_div_val3 /* rsm val */ 89 str r2, [r5] 90 ldr r5, pll_div_add4 /* gfx */ 91 ldr r2, pll_div_val4 92 str r2, [r5] 93 ldr r5, pll_div_add5 /* emu */ 94 ldr r2, pll_div_val5 95 str r2, [r5] 96 97 /* now prepare GPMC (flash) for new dpll speed */ 98 /* flash needs to be stable when we jump back to it */ 99 ldr r5, flash_cfg3_addr 100 ldr r2, flash_cfg3_val 101 str r2, [r5] 102 ldr r5, flash_cfg4_addr 103 ldr r2, flash_cfg4_val 104 str r2, [r5] 105 ldr r5, flash_cfg5_addr 106 ldr r2, flash_cfg5_val 107 str r2, [r5] 108 ldr r5, flash_cfg1_addr 109 ldr r2, [r5] 110 orr r2, r2, #0x3 /* up gpmc divider */ 111 str r2, [r5] 112 113 /* lock DPLL3 and wait a bit */ 114 orr r0, r0, #0x7 /* set up for lock mode */ 115 str r0, [r4] /* lock */ 116 nop /* ARM slow at this point working at sys_clk */ 117 nop 118 nop 119 nop 120wait2: 121 ldr r5, [r3] /* get status */ 122 and r5, r5, #0x1 /* isolate core status */ 123 cmp r5, #0x1 /* still locked? */ 124 bne wait2 /* if lock, loop */ 125 nop 126 nop 127 nop 128 nop 129 ldmfd sp!, {r4 - r6} 130 mov pc, lr /* back to caller, locked */ 131ENDPROC(go_to_speed) 132 133_go_to_speed: .word go_to_speed 134 135/* these constants need to be close for PIC code */ 136/* The Nor has to be in the Flash Base CS0 for this condition to happen */ 137flash_cfg1_addr: 138 .word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG1) 139flash_cfg3_addr: 140 .word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG3) 141flash_cfg3_val: 142 .word STNOR_GPMC_CONFIG3 143flash_cfg4_addr: 144 .word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG4) 145flash_cfg4_val: 146 .word STNOR_GPMC_CONFIG4 147flash_cfg5_val: 148 .word STNOR_GPMC_CONFIG5 149flash_cfg5_addr: 150 .word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG5) 151pll_ctl_add: 152 .word CM_CLKEN_PLL 153pll_div_add1: 154 .word CM_CLKSEL1_PLL 155pll_div_add2: 156 .word CM_CLKSEL_CORE 157pll_div_add3: 158 .word CM_CLKSEL_WKUP 159pll_div_val3: 160 .word (WKUP_RSM << 1) 161pll_div_add4: 162 .word CM_CLKSEL_GFX 163pll_div_val4: 164 .word (GFX_DIV << 0) 165pll_div_add5: 166 .word CM_CLKSEL1_EMU 167pll_div_val5: 168 .word CLSEL1_EMU_VAL 169 170go_to_speed_end: 171#endif 172 173#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) && \ 174 !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY) 175ENTRY(lowlevel_init) 176 ldr sp, SRAM_STACK 177 str ip, [sp] /* stash ip register */ 178 mov ip, lr /* save link reg across call */ 179#if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_ONENAND_BOOT) 180/* 181 * No need to copy/exec the clock code - DPLL adjust already done 182 * in NAND/oneNAND Boot. 183 */ 184 ldr r1, =SRAM_CLK_CODE 185 bl cpy_clk_code 186#endif /* NAND Boot */ 187 mov lr, ip /* restore link reg */ 188 ldr ip, [sp] /* restore save ip */ 189 /* tail-call s_init to setup pll, mux, memory */ 190 b s_init 191 192ENDPROC(lowlevel_init) 193#endif 194 195 /* the literal pools origin */ 196 .ltorg 197 198REG_CONTROL_STATUS: 199 .word CONTROL_STATUS 200SRAM_STACK: 201 .word LOW_LEVEL_SRAM_STACK 202 203/* DPLL(1-4) PARAM TABLES */ 204 205/* 206 * Each of the tables has M, N, FREQSEL, M2 values defined for nominal 207 * OPP (1.2V). The fields are defined according to dpll_param struct (clock.c). 208 * The values are defined for all possible sysclk and for ES1 and ES2. 209 */ 210 211mpu_dpll_param: 212/* 12MHz */ 213/* ES1 */ 214.word MPU_M_12_ES1, MPU_N_12_ES1, MPU_FSEL_12_ES1, MPU_M2_12_ES1 215/* ES2 */ 216.word MPU_M_12_ES2, MPU_N_12_ES2, MPU_FSEL_12_ES2, MPU_M2_ES2 217/* 3410 */ 218.word MPU_M_12, MPU_N_12, MPU_FSEL_12, MPU_M2_12 219 220/* 13MHz */ 221/* ES1 */ 222.word MPU_M_13_ES1, MPU_N_13_ES1, MPU_FSEL_13_ES1, MPU_M2_13_ES1 223/* ES2 */ 224.word MPU_M_13_ES2, MPU_N_13_ES2, MPU_FSEL_13_ES2, MPU_M2_13_ES2 225/* 3410 */ 226.word MPU_M_13, MPU_N_13, MPU_FSEL_13, MPU_M2_13 227 228/* 19.2MHz */ 229/* ES1 */ 230.word MPU_M_19P2_ES1, MPU_N_19P2_ES1, MPU_FSEL_19P2_ES1, MPU_M2_19P2_ES1 231/* ES2 */ 232.word MPU_M_19P2_ES2, MPU_N_19P2_ES2, MPU_FSEL_19P2_ES2, MPU_M2_19P2_ES2 233/* 3410 */ 234.word MPU_M_19P2, MPU_N_19P2, MPU_FSEL_19P2, MPU_M2_19P2 235 236/* 26MHz */ 237/* ES1 */ 238.word MPU_M_26_ES1, MPU_N_26_ES1, MPU_FSEL_26_ES1, MPU_M2_26_ES1 239/* ES2 */ 240.word MPU_M_26_ES2, MPU_N_26_ES2, MPU_FSEL_26_ES2, MPU_M2_26_ES2 241/* 3410 */ 242.word MPU_M_26, MPU_N_26, MPU_FSEL_26, MPU_M2_26 243 244/* 38.4MHz */ 245/* ES1 */ 246.word MPU_M_38P4_ES1, MPU_N_38P4_ES1, MPU_FSEL_38P4_ES1, MPU_M2_38P4_ES1 247/* ES2 */ 248.word MPU_M_38P4_ES2, MPU_N_38P4_ES2, MPU_FSEL_38P4_ES2, MPU_M2_38P4_ES2 249/* 3410 */ 250.word MPU_M_38P4, MPU_N_38P4, MPU_FSEL_38P4, MPU_M2_38P4 251 252 253.globl get_mpu_dpll_param 254get_mpu_dpll_param: 255 adr r0, mpu_dpll_param 256 mov pc, lr 257 258iva_dpll_param: 259/* 12MHz */ 260/* ES1 */ 261.word IVA_M_12_ES1, IVA_N_12_ES1, IVA_FSEL_12_ES1, IVA_M2_12_ES1 262/* ES2 */ 263.word IVA_M_12_ES2, IVA_N_12_ES2, IVA_FSEL_12_ES2, IVA_M2_12_ES2 264/* 3410 */ 265.word IVA_M_12, IVA_N_12, IVA_FSEL_12, IVA_M2_12 266 267/* 13MHz */ 268/* ES1 */ 269.word IVA_M_13_ES1, IVA_N_13_ES1, IVA_FSEL_13_ES1, IVA_M2_13_ES1 270/* ES2 */ 271.word IVA_M_13_ES2, IVA_N_13_ES2, IVA_FSEL_13_ES2, IVA_M2_13_ES2 272/* 3410 */ 273.word IVA_M_13, IVA_N_13, IVA_FSEL_13, IVA_M2_13 274 275/* 19.2MHz */ 276/* ES1 */ 277.word IVA_M_19P2_ES1, IVA_N_19P2_ES1, IVA_FSEL_19P2_ES1, IVA_M2_19P2_ES1 278/* ES2 */ 279.word IVA_M_19P2_ES2, IVA_N_19P2_ES2, IVA_FSEL_19P2_ES2, IVA_M2_19P2_ES2 280/* 3410 */ 281.word IVA_M_19P2, IVA_N_19P2, IVA_FSEL_19P2, IVA_M2_19P2 282 283/* 26MHz */ 284/* ES1 */ 285.word IVA_M_26_ES1, IVA_N_26_ES1, IVA_FSEL_26_ES1, IVA_M2_26_ES1 286/* ES2 */ 287.word IVA_M_26_ES2, IVA_N_26_ES2, IVA_FSEL_26_ES2, IVA_M2_26_ES2 288/* 3410 */ 289.word IVA_M_26, IVA_N_26, IVA_FSEL_26, IVA_M2_26 290 291/* 38.4MHz */ 292/* ES1 */ 293.word IVA_M_38P4_ES1, IVA_N_38P4_ES1, IVA_FSEL_38P4_ES1, IVA_M2_38P4_ES1 294/* ES2 */ 295.word IVA_M_38P4_ES2, IVA_N_38P4_ES2, IVA_FSEL_38P4_ES2, IVA_M2_38P4_ES2 296/* 3410 */ 297.word IVA_M_38P4, IVA_N_38P4, IVA_FSEL_38P4, IVA_M2_38P4 298 299 300.globl get_iva_dpll_param 301get_iva_dpll_param: 302 adr r0, iva_dpll_param 303 mov pc, lr 304 305/* Core DPLL targets for L3 at 166 & L133 */ 306core_dpll_param: 307/* 12MHz */ 308/* ES1 */ 309.word CORE_M_12_ES1, CORE_N_12_ES1, CORE_FSL_12_ES1, CORE_M2_12_ES1 310/* ES2 */ 311.word CORE_M_12, CORE_N_12, CORE_FSEL_12, CORE_M2_12 312/* 3410 */ 313.word CORE_M_12, CORE_N_12, CORE_FSEL_12, CORE_M2_12 314 315/* 13MHz */ 316/* ES1 */ 317.word CORE_M_13_ES1, CORE_N_13_ES1, CORE_FSL_13_ES1, CORE_M2_13_ES1 318/* ES2 */ 319.word CORE_M_13, CORE_N_13, CORE_FSEL_13, CORE_M2_13 320/* 3410 */ 321.word CORE_M_13, CORE_N_13, CORE_FSEL_13, CORE_M2_13 322 323/* 19.2MHz */ 324/* ES1 */ 325.word CORE_M_19P2_ES1, CORE_N_19P2_ES1, CORE_FSL_19P2_ES1, CORE_M2_19P2_ES1 326/* ES2 */ 327.word CORE_M_19P2, CORE_N_19P2, CORE_FSEL_19P2, CORE_M2_19P2 328/* 3410 */ 329.word CORE_M_19P2, CORE_N_19P2, CORE_FSEL_19P2, CORE_M2_19P2 330 331/* 26MHz */ 332/* ES1 */ 333.word CORE_M_26_ES1, CORE_N_26_ES1, CORE_FSL_26_ES1, CORE_M2_26_ES1 334/* ES2 */ 335.word CORE_M_26, CORE_N_26, CORE_FSEL_26, CORE_M2_26 336/* 3410 */ 337.word CORE_M_26, CORE_N_26, CORE_FSEL_26, CORE_M2_26 338 339/* 38.4MHz */ 340/* ES1 */ 341.word CORE_M_38P4_ES1, CORE_N_38P4_ES1, CORE_FSL_38P4_ES1, CORE_M2_38P4_ES1 342/* ES2 */ 343.word CORE_M_38P4, CORE_N_38P4, CORE_FSEL_38P4, CORE_M2_38P4 344/* 3410 */ 345.word CORE_M_38P4, CORE_N_38P4, CORE_FSEL_38P4, CORE_M2_38P4 346 347.globl get_core_dpll_param 348get_core_dpll_param: 349 adr r0, core_dpll_param 350 mov pc, lr 351 352/* PER DPLL values are same for both ES1 and ES2 */ 353per_dpll_param: 354/* 12MHz */ 355.word PER_M_12, PER_N_12, PER_FSEL_12, PER_M2_12 356 357/* 13MHz */ 358.word PER_M_13, PER_N_13, PER_FSEL_13, PER_M2_13 359 360/* 19.2MHz */ 361.word PER_M_19P2, PER_N_19P2, PER_FSEL_19P2, PER_M2_19P2 362 363/* 26MHz */ 364.word PER_M_26, PER_N_26, PER_FSEL_26, PER_M2_26 365 366/* 38.4MHz */ 367.word PER_M_38P4, PER_N_38P4, PER_FSEL_38P4, PER_M2_38P4 368 369.globl get_per_dpll_param 370get_per_dpll_param: 371 adr r0, per_dpll_param 372 mov pc, lr 373 374/* PER2 DPLL values */ 375per2_dpll_param: 376/* 12MHz */ 377.word PER2_M_12, PER2_N_12, PER2_FSEL_12, PER2_M2_12 378 379/* 13MHz */ 380.word PER2_M_13, PER2_N_13, PER2_FSEL_13, PER2_M2_13 381 382/* 19.2MHz */ 383.word PER2_M_19P2, PER2_N_19P2, PER2_FSEL_19P2, PER2_M2_19P2 384 385/* 26MHz */ 386.word PER2_M_26, PER2_N_26, PER2_FSEL_26, PER2_M2_26 387 388/* 38.4MHz */ 389.word PER2_M_38P4, PER2_N_38P4, PER2_FSEL_38P4, PER2_M2_38P4 390 391.globl get_per2_dpll_param 392get_per2_dpll_param: 393 adr r0, per2_dpll_param 394 mov pc, lr 395 396/* 397 * Tables for 36XX/37XX devices 398 * 399 */ 400mpu_36x_dpll_param: 401/* 12MHz */ 402.word 50, 0, 0, 1 403/* 13MHz */ 404.word 600, 12, 0, 1 405/* 19.2MHz */ 406.word 125, 3, 0, 1 407/* 26MHz */ 408.word 300, 12, 0, 1 409/* 38.4MHz */ 410.word 125, 7, 0, 1 411 412iva_36x_dpll_param: 413/* 12MHz */ 414.word 130, 2, 0, 1 415/* 13MHz */ 416.word 20, 0, 0, 1 417/* 19.2MHz */ 418.word 325, 11, 0, 1 419/* 26MHz */ 420.word 10, 0, 0, 1 421/* 38.4MHz */ 422.word 325, 23, 0, 1 423 424core_36x_dpll_param: 425/* 12MHz */ 426.word 100, 2, 0, 1 427/* 13MHz */ 428.word 400, 12, 0, 1 429/* 19.2MHz */ 430.word 375, 17, 0, 1 431/* 26MHz */ 432.word 200, 12, 0, 1 433/* 38.4MHz */ 434.word 375, 35, 0, 1 435 436per_36x_dpll_param: 437/* SYSCLK M N M2 M3 M4 M5 M6 m2DIV */ 438.word 12000, 360, 4, 9, 16, 5, 4, 3, 1 439.word 13000, 864, 12, 9, 16, 9, 4, 3, 1 440.word 19200, 360, 7, 9, 16, 5, 4, 3, 1 441.word 26000, 432, 12, 9, 16, 9, 4, 3, 1 442.word 38400, 360, 15, 9, 16, 5, 4, 3, 1 443 444per2_36x_dpll_param: 445/* 12MHz */ 446.word PER2_36XX_M_12, PER2_36XX_N_12, 0, PER2_36XX_M2_12 447/* 13MHz */ 448.word PER2_36XX_M_13, PER2_36XX_N_13, 0, PER2_36XX_M2_13 449/* 19.2MHz */ 450.word PER2_36XX_M_19P2, PER2_36XX_N_19P2, 0, PER2_36XX_M2_19P2 451/* 26MHz */ 452.word PER2_36XX_M_26, PER2_36XX_N_26, 0, PER2_36XX_M2_26 453/* 38.4MHz */ 454.word PER2_36XX_M_38P4, PER2_36XX_N_38P4, 0, PER2_36XX_M2_38P4 455 456 457ENTRY(get_36x_mpu_dpll_param) 458 adr r0, mpu_36x_dpll_param 459 mov pc, lr 460ENDPROC(get_36x_mpu_dpll_param) 461 462ENTRY(get_36x_iva_dpll_param) 463 adr r0, iva_36x_dpll_param 464 mov pc, lr 465ENDPROC(get_36x_iva_dpll_param) 466 467ENTRY(get_36x_core_dpll_param) 468 adr r0, core_36x_dpll_param 469 mov pc, lr 470ENDPROC(get_36x_core_dpll_param) 471 472ENTRY(get_36x_per_dpll_param) 473 adr r0, per_36x_dpll_param 474 mov pc, lr 475ENDPROC(get_36x_per_dpll_param) 476 477ENTRY(get_36x_per2_dpll_param) 478 adr r0, per2_36x_dpll_param 479 mov pc, lr 480ENDPROC(get_36x_per2_dpll_param) 481