/u-boot/lib/efi_selftest/ |
H A D | efi_selftest_mem.c | 39 u8 c1[] = "abcdefghijklmnop"; local 44 ret = boottime->calculate_crc32(c1, 16, &crc32); 53 boottime->copy_mem(&c1[5], &c1[3], 8); 54 if (memcmp(c1, "abcdedefghijknop", 16)) { 55 efi_st_error("CopyMem forward copy failed: %s\n", c1); 63 boottime->set_mem(&c1[3], 8, 'x'); 64 if (memcmp(c1, "abcxxxxxxxxjknop", 16)) { 65 efi_st_error("SetMem failed: %s\n", c1);
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H A D | efi_selftest_unicode_collation.c | 47 u16 c1[] = u"first"; local 52 c1, c2); 55 "stri_coll(\"%ps\", \"%ps\") = %d\n", c1, c2, (int)ret); 60 c1, c3); 63 "stri_coll(\"%ps\", \"%ps\") = %d\n", c1, c3, (int)ret); 68 c3, c1); 71 "stri_coll(\"%ps\", \"%ps\") = %d\n", c3, c1, (int)ret);
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/u-boot/arch/arm/mach-mediatek/mt7623/ |
H A D | lowlevel_init.S | 18 mrc p15, 0, r0, c1, c0, 1 20 mcr p15, 0, r0, c1, c0, 1
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/u-boot/arch/arm/cpu/arm11/ |
H A D | sctlr.S | 20 mrc p15, 0, r0, c1, c0, 0 @ load system control register 23 mcr p15, 0, r0, c1, c0, 0 @ write system control register
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/u-boot/arch/arm/cpu/armv7/ |
H A D | sctlr.S | 18 mrc p15, 0, r0, c1, c0, 0 @ load system control register 20 mcr p15, 0, r0, c1, c0, 0 @ write system control register
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H A D | nonsec_virt.S | 32 mrc p15, 0, \tmp, c0, c1, 1 @ read ID_PFR1 61 mrc p15, 0, r5, c1, c0, 1 63 mcr p15, 0, r5, c1, c0, 1 68 mrc p15, 0, r5, c1, c0, 1 70 mcr p15, 0, r5, c1, c0, 1 74 mrc p15, 0, r5, c1, c1, 0 @ read SCR 87 mcr p15, 0, r5, c1, c1, 0 @ write SCR (with NS bit set) 93 mrc p15, 0, r4, c0, c1, [all...] |
H A D | start.S | 83 mrc p15, 0, r0, c0, c1, 1 @ read ID_PFR1 106 mrc p15, 0, r0, c1, c0, 0 @ Read CP15 SCTLR Register 108 mcr p15, 0, r0, c1, c0, 0 @ Write CP15 SCTLR Register 208 mrc p15, 0, r0, c1, c0, 1 @ read auxilary control register 210 mcr p15, 0, r0, c1, c0, 1 @ write auxilary control register 226 mrc p15, 0, r0, c1, c0, 0 236 mcr p15, 0, r0, c1, c0, 0 239 mrc p15, 0, r0, c1, c0, 0 @ read system control register 241 mcr p15, 0, r0, c1, c0, 0 @ write system control register 315 mrc p15, 0, r0, c1, c [all...] |
/u-boot/arch/arm/mach-mediatek/mt7629/ |
H A D | lowlevel_init.S | 32 mrc p15, 0, r1, c1, c1, 0 @ Get Secure Config 34 mcr p15, 0, r0, c1, c1, 0 @ Set Non Secure bit 39 mcr p15, 0, r1, c1, c1, 0 @ Set Secure bit 44 mrc p15, 0, r0, c1, c0, 1 46 mcr p15, 0, r0, c1, c0, 1
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/u-boot/lib/bzip2/ |
H A D | bzlib_blocksort.c | 396 UChar c1, c2; local 401 c1 = block[i1]; c2 = block[i2]; 402 if (c1 != c2) return (c1 > c2); 405 c1 = block[i1]; c2 = block[i2]; 406 if (c1 != c2) return (c1 > c2); 409 c1 = block[i1]; c2 = block[i2]; 410 if (c1 != c2) return (c1 > c 805 UChar c1; local [all...] |
/u-boot/arch/arm/mach-zynq/ |
H A D | lowlevel_init.S | 13 mrc p15, 0, r1, c1, c0, 2 16 mcr p15, 0, r1, c1, c0, 2
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/u-boot/arch/arm/cpu/arm926ejs/mxs/ |
H A D | start.S | 63 /* Save control register c1 */ 64 mrc p15, 0, r2, c1, c0, 0 81 * Restore c1 register. Especially set exception vector location 85 mcr p15, 0, r2, c1, c0, 0
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/u-boot/arch/arm/cpu/arm926ejs/sunxi/ |
H A D | fel_utils.S | 19 mrc p15, 0, lr, c1, c0, 0 @ Read CP15 SCTLR Register 29 mcr p15, 0, r1, c1, c0, 0 @ Write CP15 SCTLR register
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/u-boot/arch/arm/mach-bcm283x/include/mach/ |
H A D | timer.h | 29 u32 c1; member in struct:bcm2835_timer_regs
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/u-boot/arch/arm/mach-renesas/ |
H A D | lowlevel_init_ca15.S | 48 mrceq p15, 0, r0, c1, c0, 1 /* actlr */ 50 mcreq p15, 0, r0, c1, c0, 1 73 mrc p15, 0, r0, c1, c0, 1 75 mcr p15, 0, r0, c1, c0, 1
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/u-boot/arch/arm/mach-mvebu/ |
H A D | lowlevel.S | 30 mrc p15, 0, r0, c1, c0, 0 32 mcr p15, 0, r0, c1, c0, 0
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/u-boot/arch/arm/cpu/armv7/sunxi/ |
H A D | fel_utils.S | 19 mrc p15, 0, lr, c1, c0, 0 @ Read CP15 SCTLR Register 33 mcr p15, 0, r1, c1, c0, 0 @ Write CP15 SCTLR Register
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/u-boot/arch/arm/mach-uniphier/arm32/ |
H A D | psci_smp.S | 14 mrc p15, 0, r1, c1, c0, 0 @ SCTLR (System Control Register) 17 mcr p15, 0, r1, c1, c0, 0
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H A D | lowlevel_init.S | 23 mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register) 25 mcr p15, 0, r0, c1, c0, 0 42 mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register) 44 mcr p15, 0, r0, c1, c0, 0 74 mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register) 76 mcr p15, 0, r0, c1, c0, 0
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/u-boot/arch/arm/cpu/arm1136/ |
H A D | start.S | 77 mrc p15, 0, r0, c1, c0, 0 82 mcr p15, 0, r0, c1, c0, 0
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/u-boot/arch/arm/cpu/arm946es/ |
H A D | start.S | 85 mrc p15, 0, r0, c1, c0, 0 90 mcr p15, 0, r0, c1, c0, 0
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/u-boot/arch/arm/cpu/arm1176/ |
H A D | start.S | 79 mrc p15, 0, r0, c1, c0, 0 93 mcr p15, 0, r0, c1, c0, 0
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/u-boot/arch/arm/cpu/arm920t/ |
H A D | start.S | 79 mrc p15, 0, r0, c1, c0, 0 84 mcr p15, 0, r0, c1, c0, 0
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/u-boot/arch/arm/cpu/arm926ejs/ |
H A D | start.S | 95 mrc p15, 0, r0, c1, c0, 0 107 mcr p15, 0, r0, c1, c0, 0
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/u-boot/arch/arm/mach-tegra/ |
H A D | psci.S | 41 mrc p15, 0, r5, c1, c1, 0 @ Read SCR 43 mcr p15, 0, r5, c1, c1, 0 @ Write SCR
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/u-boot/lib/efi_loader/ |
H A D | efi_unicode_collation.c | 50 s32 c1, c2; local 55 c1 = utf_to_upper(*s1); 57 if (c1 < c2) { 60 } else if (c1 > c2) {
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