1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * arch/arm/mach-renesas/lowlevel_init_ca15.S
4 *     This file is lager low level initialize.
5 *
6 * Copyright (C) 2013, 2014 Renesas Electronics Corporation
7 */
8
9#include <config.h>
10#include <linux/linkage.h>
11#include <system-constants.h>
12
13ENTRY(lowlevel_init)
14#ifndef CONFIG_SPL_BUILD
15	mrc	p15, 0, r4, c0, c0, 5 /* mpidr */
16	orr	r4, r4, r4, lsr #6
17	and	r4, r4, #7 /* id 0-3 = ca15.0,1,2,3 */
18
19	b do_lowlevel_init
20
21	.pool
22
23/*
24 * CPU ID #1-#3 come here
25 */
26	.align  4
27do_cpu_waiting:
28	ldr	r1, =0xe6180000 /* sysc */
291:	ldr	r0, [r1, #0x20] /* sbar */
30	tst	r0, r0
31	beq	1b
32	bx	r0
33
34/*
35 * Only CPU ID #0 comes here
36 */
37	.align  4
38do_lowlevel_init:
39	ldr	r2, =0xFF000044		/* PRR */
40	ldr	r1, [r2]
41	and	r1, r1, #0x7F00
42	lsrs	r1, r1, #8
43	cmp	r1, #0x4C		/* 0x4C is ID of r8a7794 */
44	beq	_enable_actlr_smp
45
46	/* surpress wfe if ca15 */
47	tst r4, #4
48	mrceq p15, 0, r0, c1, c0, 1	/* actlr */
49	orreq r0, r0, #(1<<7)
50	mcreq p15, 0, r0, c1, c0, 1
51
52	/* and set l2 latency */
53	mrc p15, 0, r0, c0, c0, 5	/* r0 = MPIDR */
54	and r0, r0, #0xf00
55	lsr r0, r0, #8
56	tst r0, #1			/* only need for cluster 0 */
57	bne _exit_init_l2_a15
58
59	mrc p15, 1, r0, c9, c0, 2	/* r0 = L2CTLR */
60	and r1, r0, #7
61	cmp r1, #3			/* has already been set up */
62	bicne r0, r0, #0xe7
63	orrne r0, r0, #0x83		/* L2CTLR[7:6] + L2CTLR[2:0] */
64#if defined(CONFIG_R8A7790)
65	orrne r0, r0, #0x20		/* L2CTLR[5] */
66#endif
67	mcrne p15, 1, r0, c9, c0, 2
68
69	b	_exit_init_l2_a15
70
71_enable_actlr_smp: /* R8A7794 only (CA7) */
72#ifndef CONFIG_DCACHE_OFF
73	mrc    p15, 0, r0, c1, c0, 1
74	orr    r0, r0, #0x40
75	mcr    p15, 0, r0, c1, c0, 1
76#endif
77
78_exit_init_l2_a15:
79	ldr	r3, =(SYS_INIT_SP_ADDR)
80	sub	sp, r3, #4
81	str	lr, [sp]
82
83	/* initialize system */
84	bl s_init
85
86	ldr	lr, [sp]
87#endif
88	mov	pc, lr
89	nop
90ENDPROC(lowlevel_init)
91	.ltorg
92