1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 *  armboot - Startup Code for ARM926EJS CPU-core
4 *
5 *  Copyright (c) 2003  Texas Instruments
6 *
7 *  ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
8 *
9 *  Copyright (c) 2001	Marius Groger <mag@sysgo.de>
10 *  Copyright (c) 2002	Alex Zupke <azu@sysgo.de>
11 *  Copyright (c) 2002	Gary Jennejohn <garyj@denx.de>
12 *  Copyright (c) 2003	Richard Woodruff <r-woodruff2@ti.com>
13 *  Copyright (c) 2003	Kshitij <kshitij@ti.com>
14 *  Copyright (c) 2010	Albert Aribaud <albert.u.boot@aribaud.net>
15 *
16 * Change to support call back into iMX28 bootrom
17 * Copyright (c) 2011 Marek Vasut <marek.vasut@gmail.com>
18 * on behalf of DENX Software Engineering GmbH
19 */
20
21#include <asm-offsets.h>
22#include <config.h>
23#include <common.h>
24#include <system-constants.h>
25
26/*
27 *************************************************************************
28 *
29 * Startup Code (reset vector)
30 *
31 * do important init only if we don't start from memory!
32 * setup Memory and board specific bits prior to relocation.
33 * relocate armboot to ram
34 * setup stack
35 *
36 *************************************************************************
37 */
38
39	.globl	reset
40reset:
41	/*
42	 * If the CPU is configured in "Wait JTAG connection mode", the stack
43	 * pointer is not configured and is zero. This will cause crash when
44	 * trying to push data onto stack right below here. Load the SP and make
45	 * it point to the end of OCRAM if the SP is zero.
46	 */
47	cmp	sp, #0x00000000
48	ldreq	sp, =SYS_INIT_SP_ADDR
49
50	/*
51	 * Store all registers on old stack pointer, this will allow us later to
52	 * return to the BootROM and let the BootROM load U-Boot into RAM.
53	 *
54	 * WARNING: Register r0 and r1 are used by the BootROM to pass data
55	 *          to the called code. Register r0 will contain arbitrary
56	 *          data that are set in the BootStream. In case this code
57	 *          was started with CALL instruction, register r1 will contain
58	 *          pointer to the return value this function can then set.
59	 *          The code below MUST NOT CHANGE register r0 and r1 !
60	 */
61	push	{r0-r12,r14}
62
63	/* Save control register c1 */
64	mrc	p15, 0, r2, c1, c0, 0
65	push	{r2}
66
67	/* Set the cpu to SVC32 mode and store old CPSR register content. */
68	mrs	r2, cpsr
69	push	{r2}
70	bic	r2, r2, #0x1f
71	orr	r2, r2, #0xd3
72	msr	cpsr, r2
73
74	bl	board_init_ll
75
76	/* Restore BootROM's CPU mode (especially FIQ). */
77	pop	{r2}
78	msr	cpsr,r2
79
80	/*
81	 * Restore c1 register. Especially set exception vector location
82	 * back to BootROM space which is required by bootrom for USB boot.
83	 */
84	pop	{r2}
85	mcr	p15, 0, r2, c1, c0, 0
86
87	pop	{r0-r12,r14}
88
89	/*
90	 * In case this code was started by the CALL instruction, the register
91	 * r0 is examined by the BootROM after this code returns. The value in
92	 * r0 must be set to 0 to indicate successful return.
93	 */
94	mov r0, #0
95
96	bx	lr
97