Searched refs:amdgpu_ring_write (Results 1 - 25 of 39) sorted by relevance

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/openbsd-current/sys/dev/pci/drm/amd/amdgpu/
H A Dvcn_sw_ring.c32 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_FENCE);
33 amdgpu_ring_write(ring, addr);
34 amdgpu_ring_write(ring, upper_32_bits(addr));
35 amdgpu_ring_write(ring, seq);
36 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_TRAP);
41 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_END);
49 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_IB);
50 amdgpu_ring_write(ring, vmid);
51 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
52 amdgpu_ring_write(rin
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H A Djpeg_v1_0.c182 amdgpu_ring_write(ring,
184 amdgpu_ring_write(ring, 0x68e04);
186 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE0));
187 amdgpu_ring_write(ring, 0x80010000);
201 amdgpu_ring_write(ring,
203 amdgpu_ring_write(ring, 0x68e04);
205 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE0));
206 amdgpu_ring_write(ring, 0x00010000);
226 amdgpu_ring_write(ring,
228 amdgpu_ring_write(rin
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H A Djpeg_v2_0.c445 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
447 amdgpu_ring_write(ring, 0x68e04);
449 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,
451 amdgpu_ring_write(ring, 0x80010000);
463 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
465 amdgpu_ring_write(ring, 0x68e04);
467 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,
469 amdgpu_ring_write(ring, 0x00010000);
487 amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_GPCOM_DATA0_INTERNAL_OFFSET,
489 amdgpu_ring_write(rin
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H A Duvd_v6_0.c183 amdgpu_ring_write(ring, HEVC_ENC_CMD_END);
486 amdgpu_ring_write(ring, tmp);
487 amdgpu_ring_write(ring, 0xFFFFF);
490 amdgpu_ring_write(ring, tmp);
491 amdgpu_ring_write(ring, 0xFFFFF);
494 amdgpu_ring_write(ring, tmp);
495 amdgpu_ring_write(ring, 0xFFFFF);
498 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0));
499 amdgpu_ring_write(ring, 0x8);
501 amdgpu_ring_write(rin
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H A Djpeg_v4_0_3.c657 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
659 amdgpu_ring_write(ring, 0x62a04); /* PCTL0_MMHUB_DEEPSLEEP_IB */
661 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,
663 amdgpu_ring_write(ring, 0x80004000);
675 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
677 amdgpu_ring_write(ring, 0x62a04);
679 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,
681 amdgpu_ring_write(ring, 0x00004000);
699 amdgpu_ring_write(ring, PACKETJ(regUVD_JPEG_GPCOM_DATA0_INTERNAL_OFFSET,
701 amdgpu_ring_write(rin
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H A Duvd_v5_0.c174 amdgpu_ring_write(ring, tmp);
175 amdgpu_ring_write(ring, 0xFFFFF);
178 amdgpu_ring_write(ring, tmp);
179 amdgpu_ring_write(ring, 0xFFFFF);
182 amdgpu_ring_write(ring, tmp);
183 amdgpu_ring_write(ring, 0xFFFFF);
186 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0));
187 amdgpu_ring_write(ring, 0x8);
189 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0));
190 amdgpu_ring_write(rin
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H A Damdgpu_uvd_v4_2.c177 amdgpu_ring_write(ring, tmp);
178 amdgpu_ring_write(ring, 0xFFFFF);
181 amdgpu_ring_write(ring, tmp);
182 amdgpu_ring_write(ring, 0xFFFFF);
185 amdgpu_ring_write(ring, tmp);
186 amdgpu_ring_write(ring, 0xFFFFF);
189 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0));
190 amdgpu_ring_write(ring, 0x8);
192 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0));
193 amdgpu_ring_write(rin
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H A Damdgpu_uvd_v3_1.c94 amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_BASE, 0));
95 amdgpu_ring_write(ring, ib->gpu_addr);
96 amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0));
97 amdgpu_ring_write(ring, ib->length_dw);
115 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
116 amdgpu_ring_write(ring, seq);
117 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
118 amdgpu_ring_write(ring, addr & 0xffffffff);
119 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
120 amdgpu_ring_write(rin
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H A Dsdma_v2_4.c230 amdgpu_ring_write(ring, ring->funcs->nop |
233 amdgpu_ring_write(ring, ring->funcs->nop);
256 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
259 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
260 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
261 amdgpu_ring_write(ring, ib->length_dw);
262 amdgpu_ring_write(ring, 0);
263 amdgpu_ring_write(ring, 0);
283 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
286 amdgpu_ring_write(rin
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H A Damdgpu_cik_sdma.c204 amdgpu_ring_write(ring, ring->funcs->nop |
207 amdgpu_ring_write(ring, ring->funcs->nop);
231 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_INDIRECT_BUFFER, 0, extra_bits));
232 amdgpu_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */
233 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xffffffff);
234 amdgpu_ring_write(ring, ib->length_dw);
256 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits));
257 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2);
258 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2);
259 amdgpu_ring_write(rin
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H A Duvd_v7_0.c191 amdgpu_ring_write(ring, HEVC_ENC_CMD_END);
553 amdgpu_ring_write(ring, tmp);
554 amdgpu_ring_write(ring, 0xFFFFF);
558 amdgpu_ring_write(ring, tmp);
559 amdgpu_ring_write(ring, 0xFFFFF);
563 amdgpu_ring_write(ring, tmp);
564 amdgpu_ring_write(ring, 0xFFFFF);
567 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, j,
569 amdgpu_ring_write(ring, 0x8);
571 amdgpu_ring_write(rin
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H A Dvcn_v2_0.c1382 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0));
1383 amdgpu_ring_write(ring, 0);
1384 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));
1385 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_START << 1));
1399 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));
1400 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_END << 1));
1419 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.nop, 0));
1420 amdgpu_ring_write(ring, 0);
1440 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.context_id, 0));
1441 amdgpu_ring_write(rin
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H A Dvcn_v1_0.c1438 amdgpu_ring_write(ring,
1440 amdgpu_ring_write(ring, 0);
1441 amdgpu_ring_write(ring,
1443 amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_START << 1);
1457 amdgpu_ring_write(ring,
1459 amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_END << 1);
1479 amdgpu_ring_write(ring,
1481 amdgpu_ring_write(ring, seq);
1482 amdgpu_ring_write(ring,
1484 amdgpu_ring_write(rin
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H A Dsdma_v3_0.c404 amdgpu_ring_write(ring, ring->funcs->nop |
407 amdgpu_ring_write(ring, ring->funcs->nop);
430 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
433 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
434 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
435 amdgpu_ring_write(ring, ib->length_dw);
436 amdgpu_ring_write(ring, 0);
437 amdgpu_ring_write(ring, 0);
457 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
460 amdgpu_ring_write(rin
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H A Dsdma_v6_0.c86 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COND_EXE));
87 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
88 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
89 amdgpu_ring_write(ring, 1);
91 amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */
231 amdgpu_ring_write(ring, ring->funcs->nop |
234 amdgpu_ring_write(ring, ring->funcs->nop);
265 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_INDIRECT) |
268 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
269 amdgpu_ring_write(rin
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H A Damdgpu_si_dma.c72 amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0));
73 amdgpu_ring_write(ring, DMA_IB_PACKET(DMA_PACKET_INDIRECT_BUFFER, vmid, 0));
74 amdgpu_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0));
75 amdgpu_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF));
97 amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0, 0, 0));
98 amdgpu_ring_write(ring, addr & 0xfffffffc);
99 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xff));
100 amdgpu_ring_write(ring, seq);
104 amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0, 0, 0));
105 amdgpu_ring_write(rin
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H A Dsdma_v5_0.c256 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE));
257 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
258 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
259 amdgpu_ring_write(ring, 1);
261 amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */
406 amdgpu_ring_write(ring, ring->funcs->nop |
409 amdgpu_ring_write(ring, ring->funcs->nop);
440 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
443 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
444 amdgpu_ring_write(rin
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H A Dsdma_v5_2.c96 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE));
97 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
98 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
99 amdgpu_ring_write(ring, 1);
101 amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */
213 amdgpu_ring_write(ring, ring->funcs->nop |
216 amdgpu_ring_write(ring, ring->funcs->nop);
247 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
250 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
251 amdgpu_ring_write(rin
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H A Dgfx_v7_0.c2039 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
2040 amdgpu_ring_write(ring, mmSCRATCH_REG0 - PACKET3_SET_UCONFIG_REG_START);
2041 amdgpu_ring_write(ring, 0xDEADBEEF);
2082 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
2083 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */
2086 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ);
2087 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE);
2088 amdgpu_ring_write(ring, ref_and_mask);
2089 amdgpu_ring_write(ring, ref_and_mask);
2090 amdgpu_ring_write(rin
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H A Dgfx_v8_0.c850 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
851 amdgpu_ring_write(ring, mmSCRATCH_REG0 - PACKET3_SET_UCONFIG_REG_START);
852 amdgpu_ring_write(ring, 0xDEADBEEF);
4161 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4162 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
4164 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
4165 amdgpu_ring_write(ring, 0x80000000);
4166 amdgpu_ring_write(ring, 0x80000000);
4171 amdgpu_ring_write(ring,
4174 amdgpu_ring_write(rin
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H A Dgfx_v9_4_3.c63 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
64 amdgpu_ring_write(kiq_ring,
68 amdgpu_ring_write(kiq_ring,
70 amdgpu_ring_write(kiq_ring,
72 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
73 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
74 amdgpu_ring_write(kiq_ring, 0); /* oac mask */
75 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
86 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
88 amdgpu_ring_write(kiq_rin
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H A Dgfx_v6_0.c1780 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1781 amdgpu_ring_write(ring, mmSCRATCH_REG0 - PACKET3_SET_CONFIG_REG_START);
1782 amdgpu_ring_write(ring, 0xDEADBEEF);
1799 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
1800 amdgpu_ring_write(ring, EVENT_TYPE(VGT_FLUSH) |
1810 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1811 amdgpu_ring_write(ring, (mmCP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START));
1812 amdgpu_ring_write(ring, 0);
1813 amdgpu_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1814 amdgpu_ring_write(rin
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H A Dgfx_v9_0.c771 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
772 amdgpu_ring_write(kiq_ring,
776 amdgpu_ring_write(kiq_ring,
778 amdgpu_ring_write(kiq_ring,
780 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
781 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
782 amdgpu_ring_write(kiq_ring, 0); /* oac mask */
783 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
793 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
795 amdgpu_ring_write(kiq_rin
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H A Dgfx_v11_0.c137 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
138 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
140 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
141 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */
142 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
143 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
144 amdgpu_ring_write(kiq_ring, 0); /* oac mask */
145 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
172 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
174 amdgpu_ring_write(kiq_rin
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H A Dsdma_v4_4_2.c293 amdgpu_ring_write(ring, ring->funcs->nop |
296 amdgpu_ring_write(ring, ring->funcs->nop);
319 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
322 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
323 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
324 amdgpu_ring_write(ring, ib->length_dw);
325 amdgpu_ring_write(ring, 0);
326 amdgpu_ring_write(ring, 0);
336 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
342 amdgpu_ring_write(rin
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