amd/amdgpu/sdma_v3_0.c

404 			amdgpu_ring_write(ring, ring->funcs->nop |
407 			amdgpu_ring_write(ring, ring->funcs->nop);
430 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
433 	amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
434 	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
435 	amdgpu_ring_write(ring, ib->length_dw);
436 	amdgpu_ring_write(ring, 0);
437 	amdgpu_ring_write(ring, 0);
457 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
460 	amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2);
461 	amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2);
462 	amdgpu_ring_write(ring, ref_and_mask); /* reference */
463 	amdgpu_ring_write(ring, ref_and_mask); /* mask */
464 	amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
485 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
486 	amdgpu_ring_write(ring, lower_32_bits(addr));
487 	amdgpu_ring_write(ring, upper_32_bits(addr));
488 	amdgpu_ring_write(ring, lower_32_bits(seq));
493 		amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
494 		amdgpu_ring_write(ring, lower_32_bits(addr));
495 		amdgpu_ring_write(ring, upper_32_bits(addr));
496 		amdgpu_ring_write(ring, upper_32_bits(seq));
500 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
501 	amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
828 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
830 	amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
831 	amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
832 	amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1));
833 	amdgpu_ring_write(ring, 0xDEADBEEF);
1039 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1043 	amdgpu_ring_write(ring, addr & 0xfffffffc);
1044 	amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1045 	amdgpu_ring_write(ring, seq); /* reference */
1046 	amdgpu_ring_write(ring, 0xffffffff); /* mask */
1047 	amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1067 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1070 	amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
1071 	amdgpu_ring_write(ring, 0);
1072 	amdgpu_ring_write(ring, 0); /* reference */
1073 	amdgpu_ring_write(ring, 0); /* mask */
1074 	amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1081 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1083 	amdgpu_ring_write(ring, reg);
1084 	amdgpu_ring_write(ring, val);