amd/amdgpu/sdma_v5_0.c

256 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE));
257 	amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
258 	amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
259 	amdgpu_ring_write(ring, 1);
261 	amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */
406 			amdgpu_ring_write(ring, ring->funcs->nop |
409 			amdgpu_ring_write(ring, ring->funcs->nop);
440 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
443 	amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
444 	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
445 	amdgpu_ring_write(ring, ib->length_dw);
446 	amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr));
447 	amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr));
464 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_GCR_REQ));
465 	amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(0));
466 	amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(gcr_cntl) |
468 	amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(0) |
470 	amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(0) |
492 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
495 	amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2);
496 	amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2);
497 	amdgpu_ring_write(ring, ref_and_mask); /* reference */
498 	amdgpu_ring_write(ring, ref_and_mask); /* mask */
499 	amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
520 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
524 	amdgpu_ring_write(ring, lower_32_bits(addr));
525 	amdgpu_ring_write(ring, upper_32_bits(addr));
526 	amdgpu_ring_write(ring, lower_32_bits(seq));
531 		amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
535 		amdgpu_ring_write(ring, lower_32_bits(addr));
536 		amdgpu_ring_write(ring, upper_32_bits(addr));
537 		amdgpu_ring_write(ring, upper_32_bits(seq));
544 		amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
545 		amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(ctx));
1023 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1025 	amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
1026 	amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
1027 	amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
1028 	amdgpu_ring_write(ring, 0xDEADBEEF);
1274 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1278 	amdgpu_ring_write(ring, addr & 0xfffffffc);
1279 	amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1280 	amdgpu_ring_write(ring, seq); /* reference */
1281 	amdgpu_ring_write(ring, 0xffffffff); /* mask */
1282 	amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1306 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1308 	amdgpu_ring_write(ring, reg);
1309 	amdgpu_ring_write(ring, val);
1315 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1318 	amdgpu_ring_write(ring, reg << 2);
1319 	amdgpu_ring_write(ring, 0);
1320 	amdgpu_ring_write(ring, val); /* reference */
1321 	amdgpu_ring_write(ring, mask); /* mask */
1322 	amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |