1/* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24#include <linux/firmware.h> 25 26#include "amdgpu.h" 27#include "amdgpu_uvd.h" 28#include "amdgpu_cs.h" 29#include "soc15.h" 30#include "soc15d.h" 31#include "soc15_common.h" 32#include "mmsch_v1_0.h" 33 34#include "uvd/uvd_7_0_offset.h" 35#include "uvd/uvd_7_0_sh_mask.h" 36#include "vce/vce_4_0_offset.h" 37#include "vce/vce_4_0_default.h" 38#include "vce/vce_4_0_sh_mask.h" 39#include "nbif/nbif_6_1_offset.h" 40#include "mmhub/mmhub_1_0_offset.h" 41#include "mmhub/mmhub_1_0_sh_mask.h" 42#include "ivsrcid/uvd/irqsrcs_uvd_7_0.h" 43 44#define mmUVD_PG0_CC_UVD_HARVESTING 0x00c7 45#define mmUVD_PG0_CC_UVD_HARVESTING_BASE_IDX 1 46//UVD_PG0_CC_UVD_HARVESTING 47#define UVD_PG0_CC_UVD_HARVESTING__UVD_DISABLE__SHIFT 0x1 48#define UVD_PG0_CC_UVD_HARVESTING__UVD_DISABLE_MASK 0x00000002L 49 50#define UVD7_MAX_HW_INSTANCES_VEGA20 2 51 52static void uvd_v7_0_set_ring_funcs(struct amdgpu_device *adev); 53static void uvd_v7_0_set_enc_ring_funcs(struct amdgpu_device *adev); 54static void uvd_v7_0_set_irq_funcs(struct amdgpu_device *adev); 55static int uvd_v7_0_start(struct amdgpu_device *adev); 56static void uvd_v7_0_stop(struct amdgpu_device *adev); 57static int uvd_v7_0_sriov_start(struct amdgpu_device *adev); 58 59static int amdgpu_ih_clientid_uvds[] = { 60 SOC15_IH_CLIENTID_UVD, 61 SOC15_IH_CLIENTID_UVD1 62}; 63 64/** 65 * uvd_v7_0_ring_get_rptr - get read pointer 66 * 67 * @ring: amdgpu_ring pointer 68 * 69 * Returns the current hardware read pointer 70 */ 71static uint64_t uvd_v7_0_ring_get_rptr(struct amdgpu_ring *ring) 72{ 73 struct amdgpu_device *adev = ring->adev; 74 75 return RREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_RPTR); 76} 77 78/** 79 * uvd_v7_0_enc_ring_get_rptr - get enc read pointer 80 * 81 * @ring: amdgpu_ring pointer 82 * 83 * Returns the current hardware enc read pointer 84 */ 85static uint64_t uvd_v7_0_enc_ring_get_rptr(struct amdgpu_ring *ring) 86{ 87 struct amdgpu_device *adev = ring->adev; 88 89 if (ring == &adev->uvd.inst[ring->me].ring_enc[0]) 90 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_RPTR); 91 else 92 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_RPTR2); 93} 94 95/** 96 * uvd_v7_0_ring_get_wptr - get write pointer 97 * 98 * @ring: amdgpu_ring pointer 99 * 100 * Returns the current hardware write pointer 101 */ 102static uint64_t uvd_v7_0_ring_get_wptr(struct amdgpu_ring *ring) 103{ 104 struct amdgpu_device *adev = ring->adev; 105 106 return RREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR); 107} 108 109/** 110 * uvd_v7_0_enc_ring_get_wptr - get enc write pointer 111 * 112 * @ring: amdgpu_ring pointer 113 * 114 * Returns the current hardware enc write pointer 115 */ 116static uint64_t uvd_v7_0_enc_ring_get_wptr(struct amdgpu_ring *ring) 117{ 118 struct amdgpu_device *adev = ring->adev; 119 120 if (ring->use_doorbell) 121 return *ring->wptr_cpu_addr; 122 123 if (ring == &adev->uvd.inst[ring->me].ring_enc[0]) 124 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR); 125 else 126 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR2); 127} 128 129/** 130 * uvd_v7_0_ring_set_wptr - set write pointer 131 * 132 * @ring: amdgpu_ring pointer 133 * 134 * Commits the write pointer to the hardware 135 */ 136static void uvd_v7_0_ring_set_wptr(struct amdgpu_ring *ring) 137{ 138 struct amdgpu_device *adev = ring->adev; 139 140 WREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); 141} 142 143/** 144 * uvd_v7_0_enc_ring_set_wptr - set enc write pointer 145 * 146 * @ring: amdgpu_ring pointer 147 * 148 * Commits the enc write pointer to the hardware 149 */ 150static void uvd_v7_0_enc_ring_set_wptr(struct amdgpu_ring *ring) 151{ 152 struct amdgpu_device *adev = ring->adev; 153 154 if (ring->use_doorbell) { 155 /* XXX check if swapping is necessary on BE */ 156 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 157 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 158 return; 159 } 160 161 if (ring == &adev->uvd.inst[ring->me].ring_enc[0]) 162 WREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR, 163 lower_32_bits(ring->wptr)); 164 else 165 WREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR2, 166 lower_32_bits(ring->wptr)); 167} 168 169/** 170 * uvd_v7_0_enc_ring_test_ring - test if UVD ENC ring is working 171 * 172 * @ring: the engine to test on 173 * 174 */ 175static int uvd_v7_0_enc_ring_test_ring(struct amdgpu_ring *ring) 176{ 177 struct amdgpu_device *adev = ring->adev; 178 uint32_t rptr; 179 unsigned i; 180 int r; 181 182 if (amdgpu_sriov_vf(adev)) 183 return 0; 184 185 r = amdgpu_ring_alloc(ring, 16); 186 if (r) 187 return r; 188 189 rptr = amdgpu_ring_get_rptr(ring); 190 191 amdgpu_ring_write(ring, HEVC_ENC_CMD_END); 192 amdgpu_ring_commit(ring); 193 194 for (i = 0; i < adev->usec_timeout; i++) { 195 if (amdgpu_ring_get_rptr(ring) != rptr) 196 break; 197 udelay(1); 198 } 199 200 if (i >= adev->usec_timeout) 201 r = -ETIMEDOUT; 202 203 return r; 204} 205 206/** 207 * uvd_v7_0_enc_get_create_msg - generate a UVD ENC create msg 208 * 209 * @ring: ring we should submit the msg to 210 * @handle: session handle to use 211 * @bo: amdgpu object for which we query the offset 212 * @fence: optional fence to return 213 * 214 * Open up a stream for HW test 215 */ 216static int uvd_v7_0_enc_get_create_msg(struct amdgpu_ring *ring, u32 handle, 217 struct amdgpu_bo *bo, 218 struct dma_fence **fence) 219{ 220 const unsigned ib_size_dw = 16; 221 struct amdgpu_job *job; 222 struct amdgpu_ib *ib; 223 struct dma_fence *f = NULL; 224 uint64_t addr; 225 int i, r; 226 227 r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, ib_size_dw * 4, 228 AMDGPU_IB_POOL_DIRECT, &job); 229 if (r) 230 return r; 231 232 ib = &job->ibs[0]; 233 addr = amdgpu_bo_gpu_offset(bo); 234 235 ib->length_dw = 0; 236 ib->ptr[ib->length_dw++] = 0x00000018; 237 ib->ptr[ib->length_dw++] = 0x00000001; /* session info */ 238 ib->ptr[ib->length_dw++] = handle; 239 ib->ptr[ib->length_dw++] = 0x00000000; 240 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 241 ib->ptr[ib->length_dw++] = addr; 242 243 ib->ptr[ib->length_dw++] = 0x00000014; 244 ib->ptr[ib->length_dw++] = 0x00000002; /* task info */ 245 ib->ptr[ib->length_dw++] = 0x0000001c; 246 ib->ptr[ib->length_dw++] = 0x00000000; 247 ib->ptr[ib->length_dw++] = 0x00000000; 248 249 ib->ptr[ib->length_dw++] = 0x00000008; 250 ib->ptr[ib->length_dw++] = 0x08000001; /* op initialize */ 251 252 for (i = ib->length_dw; i < ib_size_dw; ++i) 253 ib->ptr[i] = 0x0; 254 255 r = amdgpu_job_submit_direct(job, ring, &f); 256 if (r) 257 goto err; 258 259 if (fence) 260 *fence = dma_fence_get(f); 261 dma_fence_put(f); 262 return 0; 263 264err: 265 amdgpu_job_free(job); 266 return r; 267} 268 269/** 270 * uvd_v7_0_enc_get_destroy_msg - generate a UVD ENC destroy msg 271 * 272 * @ring: ring we should submit the msg to 273 * @handle: session handle to use 274 * @bo: amdgpu object for which we query the offset 275 * @fence: optional fence to return 276 * 277 * Close up a stream for HW test or if userspace failed to do so 278 */ 279static int uvd_v7_0_enc_get_destroy_msg(struct amdgpu_ring *ring, u32 handle, 280 struct amdgpu_bo *bo, 281 struct dma_fence **fence) 282{ 283 const unsigned ib_size_dw = 16; 284 struct amdgpu_job *job; 285 struct amdgpu_ib *ib; 286 struct dma_fence *f = NULL; 287 uint64_t addr; 288 int i, r; 289 290 r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, ib_size_dw * 4, 291 AMDGPU_IB_POOL_DIRECT, &job); 292 if (r) 293 return r; 294 295 ib = &job->ibs[0]; 296 addr = amdgpu_bo_gpu_offset(bo); 297 298 ib->length_dw = 0; 299 ib->ptr[ib->length_dw++] = 0x00000018; 300 ib->ptr[ib->length_dw++] = 0x00000001; 301 ib->ptr[ib->length_dw++] = handle; 302 ib->ptr[ib->length_dw++] = 0x00000000; 303 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 304 ib->ptr[ib->length_dw++] = addr; 305 306 ib->ptr[ib->length_dw++] = 0x00000014; 307 ib->ptr[ib->length_dw++] = 0x00000002; 308 ib->ptr[ib->length_dw++] = 0x0000001c; 309 ib->ptr[ib->length_dw++] = 0x00000000; 310 ib->ptr[ib->length_dw++] = 0x00000000; 311 312 ib->ptr[ib->length_dw++] = 0x00000008; 313 ib->ptr[ib->length_dw++] = 0x08000002; /* op close session */ 314 315 for (i = ib->length_dw; i < ib_size_dw; ++i) 316 ib->ptr[i] = 0x0; 317 318 r = amdgpu_job_submit_direct(job, ring, &f); 319 if (r) 320 goto err; 321 322 if (fence) 323 *fence = dma_fence_get(f); 324 dma_fence_put(f); 325 return 0; 326 327err: 328 amdgpu_job_free(job); 329 return r; 330} 331 332/** 333 * uvd_v7_0_enc_ring_test_ib - test if UVD ENC IBs are working 334 * 335 * @ring: the engine to test on 336 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT 337 * 338 */ 339static int uvd_v7_0_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout) 340{ 341 struct dma_fence *fence = NULL; 342 struct amdgpu_bo *bo = ring->adev->uvd.ib_bo; 343 long r; 344 345 r = uvd_v7_0_enc_get_create_msg(ring, 1, bo, NULL); 346 if (r) 347 goto error; 348 349 r = uvd_v7_0_enc_get_destroy_msg(ring, 1, bo, &fence); 350 if (r) 351 goto error; 352 353 r = dma_fence_wait_timeout(fence, false, timeout); 354 if (r == 0) 355 r = -ETIMEDOUT; 356 else if (r > 0) 357 r = 0; 358 359error: 360 dma_fence_put(fence); 361 return r; 362} 363 364static int uvd_v7_0_early_init(void *handle) 365{ 366 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 367 368 if (adev->asic_type == CHIP_VEGA20) { 369 u32 harvest; 370 int i; 371 372 adev->uvd.num_uvd_inst = UVD7_MAX_HW_INSTANCES_VEGA20; 373 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 374 harvest = RREG32_SOC15(UVD, i, mmUVD_PG0_CC_UVD_HARVESTING); 375 if (harvest & UVD_PG0_CC_UVD_HARVESTING__UVD_DISABLE_MASK) { 376 adev->uvd.harvest_config |= 1 << i; 377 } 378 } 379 if (adev->uvd.harvest_config == (AMDGPU_UVD_HARVEST_UVD0 | 380 AMDGPU_UVD_HARVEST_UVD1)) 381 /* both instances are harvested, disable the block */ 382 return -ENOENT; 383 } else { 384 adev->uvd.num_uvd_inst = 1; 385 } 386 387 if (amdgpu_sriov_vf(adev)) 388 adev->uvd.num_enc_rings = 1; 389 else 390 adev->uvd.num_enc_rings = 2; 391 uvd_v7_0_set_ring_funcs(adev); 392 uvd_v7_0_set_enc_ring_funcs(adev); 393 uvd_v7_0_set_irq_funcs(adev); 394 395 return 0; 396} 397 398static int uvd_v7_0_sw_init(void *handle) 399{ 400 struct amdgpu_ring *ring; 401 402 int i, j, r; 403 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 404 405 for (j = 0; j < adev->uvd.num_uvd_inst; j++) { 406 if (adev->uvd.harvest_config & (1 << j)) 407 continue; 408 /* UVD TRAP */ 409 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_uvds[j], UVD_7_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->uvd.inst[j].irq); 410 if (r) 411 return r; 412 413 /* UVD ENC TRAP */ 414 for (i = 0; i < adev->uvd.num_enc_rings; ++i) { 415 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_uvds[j], i + UVD_7_0__SRCID__UVD_ENC_GEN_PURP, &adev->uvd.inst[j].irq); 416 if (r) 417 return r; 418 } 419 } 420 421 r = amdgpu_uvd_sw_init(adev); 422 if (r) 423 return r; 424 425 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 426 const struct common_firmware_header *hdr; 427 hdr = (const struct common_firmware_header *)adev->uvd.fw->data; 428 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].ucode_id = AMDGPU_UCODE_ID_UVD; 429 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].fw = adev->uvd.fw; 430 adev->firmware.fw_size += 431 ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE); 432 433 if (adev->uvd.num_uvd_inst == UVD7_MAX_HW_INSTANCES_VEGA20) { 434 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD1].ucode_id = AMDGPU_UCODE_ID_UVD1; 435 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD1].fw = adev->uvd.fw; 436 adev->firmware.fw_size += 437 ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE); 438 } 439 DRM_INFO("PSP loading UVD firmware\n"); 440 } 441 442 for (j = 0; j < adev->uvd.num_uvd_inst; j++) { 443 if (adev->uvd.harvest_config & (1 << j)) 444 continue; 445 if (!amdgpu_sriov_vf(adev)) { 446 ring = &adev->uvd.inst[j].ring; 447 ring->vm_hub = AMDGPU_MMHUB0(0); 448 snprintf(ring->name, sizeof(ring->name), "uvd_%d", ring->me); 449 r = amdgpu_ring_init(adev, ring, 512, 450 &adev->uvd.inst[j].irq, 0, 451 AMDGPU_RING_PRIO_DEFAULT, NULL); 452 if (r) 453 return r; 454 } 455 456 for (i = 0; i < adev->uvd.num_enc_rings; ++i) { 457 ring = &adev->uvd.inst[j].ring_enc[i]; 458 ring->vm_hub = AMDGPU_MMHUB0(0); 459 snprintf(ring->name, sizeof(ring->name), "uvd_enc_%d.%d", ring->me, i); 460 if (amdgpu_sriov_vf(adev)) { 461 ring->use_doorbell = true; 462 463 /* currently only use the first enconding ring for 464 * sriov, so set unused location for other unused rings. 465 */ 466 if (i == 0) 467 ring->doorbell_index = adev->doorbell_index.uvd_vce.uvd_ring0_1 * 2; 468 else 469 ring->doorbell_index = adev->doorbell_index.uvd_vce.uvd_ring2_3 * 2 + 1; 470 } 471 r = amdgpu_ring_init(adev, ring, 512, 472 &adev->uvd.inst[j].irq, 0, 473 AMDGPU_RING_PRIO_DEFAULT, NULL); 474 if (r) 475 return r; 476 } 477 } 478 479 r = amdgpu_uvd_resume(adev); 480 if (r) 481 return r; 482 483 r = amdgpu_uvd_entity_init(adev); 484 if (r) 485 return r; 486 487 r = amdgpu_virt_alloc_mm_table(adev); 488 if (r) 489 return r; 490 491 return r; 492} 493 494static int uvd_v7_0_sw_fini(void *handle) 495{ 496 int i, j, r; 497 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 498 499 amdgpu_virt_free_mm_table(adev); 500 501 r = amdgpu_uvd_suspend(adev); 502 if (r) 503 return r; 504 505 for (j = 0; j < adev->uvd.num_uvd_inst; ++j) { 506 if (adev->uvd.harvest_config & (1 << j)) 507 continue; 508 for (i = 0; i < adev->uvd.num_enc_rings; ++i) 509 amdgpu_ring_fini(&adev->uvd.inst[j].ring_enc[i]); 510 } 511 return amdgpu_uvd_sw_fini(adev); 512} 513 514/** 515 * uvd_v7_0_hw_init - start and test UVD block 516 * 517 * @handle: handle used to pass amdgpu_device pointer 518 * 519 * Initialize the hardware, boot up the VCPU and do some testing 520 */ 521static int uvd_v7_0_hw_init(void *handle) 522{ 523 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 524 struct amdgpu_ring *ring; 525 uint32_t tmp; 526 int i, j, r; 527 528 if (amdgpu_sriov_vf(adev)) 529 r = uvd_v7_0_sriov_start(adev); 530 else 531 r = uvd_v7_0_start(adev); 532 if (r) 533 goto done; 534 535 for (j = 0; j < adev->uvd.num_uvd_inst; ++j) { 536 if (adev->uvd.harvest_config & (1 << j)) 537 continue; 538 ring = &adev->uvd.inst[j].ring; 539 540 if (!amdgpu_sriov_vf(adev)) { 541 r = amdgpu_ring_test_helper(ring); 542 if (r) 543 goto done; 544 545 r = amdgpu_ring_alloc(ring, 10); 546 if (r) { 547 DRM_ERROR("amdgpu: (%d)ring failed to lock UVD ring (%d).\n", j, r); 548 goto done; 549 } 550 551 tmp = PACKET0(SOC15_REG_OFFSET(UVD, j, 552 mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL), 0); 553 amdgpu_ring_write(ring, tmp); 554 amdgpu_ring_write(ring, 0xFFFFF); 555 556 tmp = PACKET0(SOC15_REG_OFFSET(UVD, j, 557 mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL), 0); 558 amdgpu_ring_write(ring, tmp); 559 amdgpu_ring_write(ring, 0xFFFFF); 560 561 tmp = PACKET0(SOC15_REG_OFFSET(UVD, j, 562 mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL), 0); 563 amdgpu_ring_write(ring, tmp); 564 amdgpu_ring_write(ring, 0xFFFFF); 565 566 /* Clear timeout status bits */ 567 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, j, 568 mmUVD_SEMA_TIMEOUT_STATUS), 0)); 569 amdgpu_ring_write(ring, 0x8); 570 571 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, j, 572 mmUVD_SEMA_CNTL), 0)); 573 amdgpu_ring_write(ring, 3); 574 575 amdgpu_ring_commit(ring); 576 } 577 578 for (i = 0; i < adev->uvd.num_enc_rings; ++i) { 579 ring = &adev->uvd.inst[j].ring_enc[i]; 580 r = amdgpu_ring_test_helper(ring); 581 if (r) 582 goto done; 583 } 584 } 585done: 586 if (!r) 587 DRM_INFO("UVD and UVD ENC initialized successfully.\n"); 588 589 return r; 590} 591 592/** 593 * uvd_v7_0_hw_fini - stop the hardware block 594 * 595 * @handle: handle used to pass amdgpu_device pointer 596 * 597 * Stop the UVD block, mark ring as not ready any more 598 */ 599static int uvd_v7_0_hw_fini(void *handle) 600{ 601 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 602 603 cancel_delayed_work_sync(&adev->uvd.idle_work); 604 605 if (!amdgpu_sriov_vf(adev)) 606 uvd_v7_0_stop(adev); 607 else { 608 /* full access mode, so don't touch any UVD register */ 609 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n"); 610 } 611 612 return 0; 613} 614 615static int uvd_v7_0_suspend(void *handle) 616{ 617 int r; 618 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 619 620 /* 621 * Proper cleanups before halting the HW engine: 622 * - cancel the delayed idle work 623 * - enable powergating 624 * - enable clockgating 625 * - disable dpm 626 * 627 * TODO: to align with the VCN implementation, move the 628 * jobs for clockgating/powergating/dpm setting to 629 * ->set_powergating_state(). 630 */ 631 cancel_delayed_work_sync(&adev->uvd.idle_work); 632 633 if (adev->pm.dpm_enabled) { 634 amdgpu_dpm_enable_uvd(adev, false); 635 } else { 636 amdgpu_asic_set_uvd_clocks(adev, 0, 0); 637 /* shutdown the UVD block */ 638 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, 639 AMD_PG_STATE_GATE); 640 amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD, 641 AMD_CG_STATE_GATE); 642 } 643 644 r = uvd_v7_0_hw_fini(adev); 645 if (r) 646 return r; 647 648 return amdgpu_uvd_suspend(adev); 649} 650 651static int uvd_v7_0_resume(void *handle) 652{ 653 int r; 654 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 655 656 r = amdgpu_uvd_resume(adev); 657 if (r) 658 return r; 659 660 return uvd_v7_0_hw_init(adev); 661} 662 663/** 664 * uvd_v7_0_mc_resume - memory controller programming 665 * 666 * @adev: amdgpu_device pointer 667 * 668 * Let the UVD memory controller know it's offsets 669 */ 670static void uvd_v7_0_mc_resume(struct amdgpu_device *adev) 671{ 672 uint32_t size = AMDGPU_UVD_FIRMWARE_SIZE(adev); 673 uint32_t offset; 674 int i; 675 676 for (i = 0; i < adev->uvd.num_uvd_inst; ++i) { 677 if (adev->uvd.harvest_config & (1 << i)) 678 continue; 679 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 680 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 681 i == 0 ? 682 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].tmr_mc_addr_lo : 683 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD1].tmr_mc_addr_lo); 684 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 685 i == 0 ? 686 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].tmr_mc_addr_hi : 687 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD1].tmr_mc_addr_hi); 688 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET0, 0); 689 offset = 0; 690 } else { 691 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 692 lower_32_bits(adev->uvd.inst[i].gpu_addr)); 693 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 694 upper_32_bits(adev->uvd.inst[i].gpu_addr)); 695 offset = size; 696 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET0, 697 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 698 } 699 700 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE0, size); 701 702 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 703 lower_32_bits(adev->uvd.inst[i].gpu_addr + offset)); 704 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 705 upper_32_bits(adev->uvd.inst[i].gpu_addr + offset)); 706 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET1, (1 << 21)); 707 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_UVD_HEAP_SIZE); 708 709 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, 710 lower_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE)); 711 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 712 upper_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE)); 713 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET2, (2 << 21)); 714 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE2, 715 AMDGPU_UVD_STACK_SIZE + (AMDGPU_UVD_SESSION_SIZE * 40)); 716 717 WREG32_SOC15(UVD, i, mmUVD_UDEC_ADDR_CONFIG, 718 adev->gfx.config.gb_addr_config); 719 WREG32_SOC15(UVD, i, mmUVD_UDEC_DB_ADDR_CONFIG, 720 adev->gfx.config.gb_addr_config); 721 WREG32_SOC15(UVD, i, mmUVD_UDEC_DBW_ADDR_CONFIG, 722 adev->gfx.config.gb_addr_config); 723 724 WREG32_SOC15(UVD, i, mmUVD_GP_SCRATCH4, adev->uvd.max_handles); 725 } 726} 727 728static int uvd_v7_0_mmsch_start(struct amdgpu_device *adev, 729 struct amdgpu_mm_table *table) 730{ 731 uint32_t data = 0, loop; 732 uint64_t addr = table->gpu_addr; 733 struct mmsch_v1_0_init_header *header = (struct mmsch_v1_0_init_header *)table->cpu_addr; 734 uint32_t size; 735 int i; 736 737 size = header->header_size + header->vce_table_size + header->uvd_table_size; 738 739 /* 1, write to vce_mmsch_vf_ctx_addr_lo/hi register with GPU mc addr of memory descriptor location */ 740 WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_CTX_ADDR_LO, lower_32_bits(addr)); 741 WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_CTX_ADDR_HI, upper_32_bits(addr)); 742 743 /* 2, update vmid of descriptor */ 744 data = RREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_VMID); 745 data &= ~VCE_MMSCH_VF_VMID__VF_CTX_VMID_MASK; 746 data |= (0 << VCE_MMSCH_VF_VMID__VF_CTX_VMID__SHIFT); /* use domain0 for MM scheduler */ 747 WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_VMID, data); 748 749 /* 3, notify mmsch about the size of this descriptor */ 750 WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_CTX_SIZE, size); 751 752 /* 4, set resp to zero */ 753 WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP, 0); 754 755 for (i = 0; i < adev->uvd.num_uvd_inst; ++i) { 756 if (adev->uvd.harvest_config & (1 << i)) 757 continue; 758 WDOORBELL32(adev->uvd.inst[i].ring_enc[0].doorbell_index, 0); 759 *adev->uvd.inst[i].ring_enc[0].wptr_cpu_addr = 0; 760 adev->uvd.inst[i].ring_enc[0].wptr = 0; 761 adev->uvd.inst[i].ring_enc[0].wptr_old = 0; 762 } 763 /* 5, kick off the initialization and wait until VCE_MMSCH_VF_MAILBOX_RESP becomes non-zero */ 764 WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_HOST, 0x10000001); 765 766 data = RREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP); 767 loop = 1000; 768 while ((data & 0x10000002) != 0x10000002) { 769 udelay(10); 770 data = RREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP); 771 loop--; 772 if (!loop) 773 break; 774 } 775 776 if (!loop) { 777 dev_err(adev->dev, "failed to init MMSCH, mmVCE_MMSCH_VF_MAILBOX_RESP = %x\n", data); 778 return -EBUSY; 779 } 780 781 return 0; 782} 783 784static int uvd_v7_0_sriov_start(struct amdgpu_device *adev) 785{ 786 struct amdgpu_ring *ring; 787 uint32_t offset, size, tmp; 788 uint32_t table_size = 0; 789 struct mmsch_v1_0_cmd_direct_write direct_wt = { {0} }; 790 struct mmsch_v1_0_cmd_direct_read_modify_write direct_rd_mod_wt = { {0} }; 791 struct mmsch_v1_0_cmd_direct_polling direct_poll = { {0} }; 792 struct mmsch_v1_0_cmd_end end = { {0} }; 793 uint32_t *init_table = adev->virt.mm_table.cpu_addr; 794 struct mmsch_v1_0_init_header *header = (struct mmsch_v1_0_init_header *)init_table; 795 uint8_t i = 0; 796 797 direct_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_WRITE; 798 direct_rd_mod_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE; 799 direct_poll.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_POLLING; 800 end.cmd_header.command_type = MMSCH_COMMAND__END; 801 802 if (header->uvd_table_offset == 0 && header->uvd_table_size == 0) { 803 header->version = MMSCH_VERSION; 804 header->header_size = sizeof(struct mmsch_v1_0_init_header) >> 2; 805 806 if (header->vce_table_offset == 0 && header->vce_table_size == 0) 807 header->uvd_table_offset = header->header_size; 808 else 809 header->uvd_table_offset = header->vce_table_size + header->vce_table_offset; 810 811 init_table += header->uvd_table_offset; 812 813 for (i = 0; i < adev->uvd.num_uvd_inst; ++i) { 814 if (adev->uvd.harvest_config & (1 << i)) 815 continue; 816 ring = &adev->uvd.inst[i].ring; 817 ring->wptr = 0; 818 size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4); 819 820 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS), 821 0xFFFFFFFF, 0x00000004); 822 /* mc resume*/ 823 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 824 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, 825 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 826 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].tmr_mc_addr_lo); 827 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, 828 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 829 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].tmr_mc_addr_hi); 830 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0); 831 offset = 0; 832 } else { 833 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 834 lower_32_bits(adev->uvd.inst[i].gpu_addr)); 835 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 836 upper_32_bits(adev->uvd.inst[i].gpu_addr)); 837 offset = size; 838 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 839 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 840 841 } 842 843 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE0), size); 844 845 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 846 lower_32_bits(adev->uvd.inst[i].gpu_addr + offset)); 847 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 848 upper_32_bits(adev->uvd.inst[i].gpu_addr + offset)); 849 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET1), (1 << 21)); 850 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_UVD_HEAP_SIZE); 851 852 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 853 lower_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE)); 854 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 855 upper_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE)); 856 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET2), (2 << 21)); 857 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE2), 858 AMDGPU_UVD_STACK_SIZE + (AMDGPU_UVD_SESSION_SIZE * 40)); 859 860 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_GP_SCRATCH4), adev->uvd.max_handles); 861 /* mc resume end*/ 862 863 /* disable clock gating */ 864 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_CGC_CTRL), 865 ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK, 0); 866 867 /* disable interupt */ 868 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_MASTINT_EN), 869 ~UVD_MASTINT_EN__VCPU_EN_MASK, 0); 870 871 /* stall UMC and register bus before resetting VCPU */ 872 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2), 873 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, 874 UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 875 876 /* put LMI, VCPU, RBC etc... into reset */ 877 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_SOFT_RESET), 878 (uint32_t)(UVD_SOFT_RESET__LMI_SOFT_RESET_MASK | 879 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK | 880 UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK | 881 UVD_SOFT_RESET__RBC_SOFT_RESET_MASK | 882 UVD_SOFT_RESET__CSM_SOFT_RESET_MASK | 883 UVD_SOFT_RESET__CXW_SOFT_RESET_MASK | 884 UVD_SOFT_RESET__TAP_SOFT_RESET_MASK | 885 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK)); 886 887 /* initialize UVD memory controller */ 888 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL), 889 (uint32_t)((0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 890 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 891 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 892 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 893 UVD_LMI_CTRL__REQ_MODE_MASK | 894 0x00100000L)); 895 896 /* take all subblocks out of reset, except VCPU */ 897 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_SOFT_RESET), 898 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 899 900 /* enable VCPU clock */ 901 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL), 902 UVD_VCPU_CNTL__CLK_EN_MASK); 903 904 /* enable master interrupt */ 905 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_MASTINT_EN), 906 ~(UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK), 907 (UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK)); 908 909 /* clear the bit 4 of UVD_STATUS */ 910 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS), 911 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT), 0); 912 913 /* force RBC into idle state */ 914 size = order_base_2(ring->ring_size); 915 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, size); 916 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 917 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RBC_RB_CNTL), tmp); 918 919 ring = &adev->uvd.inst[i].ring_enc[0]; 920 ring->wptr = 0; 921 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_LO), ring->gpu_addr); 922 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_HI), upper_32_bits(ring->gpu_addr)); 923 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_SIZE), ring->ring_size / 4); 924 925 /* boot up the VCPU */ 926 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_SOFT_RESET), 0); 927 928 /* enable UMC */ 929 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2), 930 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, 0); 931 932 MMSCH_V1_0_INSERT_DIRECT_POLL(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS), 0x02, 0x02); 933 } 934 /* add end packet */ 935 memcpy((void *)init_table, &end, sizeof(struct mmsch_v1_0_cmd_end)); 936 table_size += sizeof(struct mmsch_v1_0_cmd_end) / 4; 937 header->uvd_table_size = table_size; 938 939 } 940 return uvd_v7_0_mmsch_start(adev, &adev->virt.mm_table); 941} 942 943/** 944 * uvd_v7_0_start - start UVD block 945 * 946 * @adev: amdgpu_device pointer 947 * 948 * Setup and start the UVD block 949 */ 950static int uvd_v7_0_start(struct amdgpu_device *adev) 951{ 952 struct amdgpu_ring *ring; 953 uint32_t rb_bufsz, tmp; 954 uint32_t lmi_swap_cntl; 955 uint32_t mp_swap_cntl; 956 int i, j, k, r; 957 958 for (k = 0; k < adev->uvd.num_uvd_inst; ++k) { 959 if (adev->uvd.harvest_config & (1 << k)) 960 continue; 961 /* disable DPG */ 962 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_POWER_STATUS), 0, 963 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); 964 } 965 966 /* disable byte swapping */ 967 lmi_swap_cntl = 0; 968 mp_swap_cntl = 0; 969 970 uvd_v7_0_mc_resume(adev); 971 972 for (k = 0; k < adev->uvd.num_uvd_inst; ++k) { 973 if (adev->uvd.harvest_config & (1 << k)) 974 continue; 975 ring = &adev->uvd.inst[k].ring; 976 /* disable clock gating */ 977 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_CGC_CTRL), 0, 978 ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK); 979 980 /* disable interupt */ 981 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_MASTINT_EN), 0, 982 ~UVD_MASTINT_EN__VCPU_EN_MASK); 983 984 /* stall UMC and register bus before resetting VCPU */ 985 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_LMI_CTRL2), 986 UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, 987 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 988 mdelay(1); 989 990 /* put LMI, VCPU, RBC etc... into reset */ 991 WREG32_SOC15(UVD, k, mmUVD_SOFT_RESET, 992 UVD_SOFT_RESET__LMI_SOFT_RESET_MASK | 993 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK | 994 UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK | 995 UVD_SOFT_RESET__RBC_SOFT_RESET_MASK | 996 UVD_SOFT_RESET__CSM_SOFT_RESET_MASK | 997 UVD_SOFT_RESET__CXW_SOFT_RESET_MASK | 998 UVD_SOFT_RESET__TAP_SOFT_RESET_MASK | 999 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); 1000 mdelay(5); 1001 1002 /* initialize UVD memory controller */ 1003 WREG32_SOC15(UVD, k, mmUVD_LMI_CTRL, 1004 (0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 1005 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 1006 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 1007 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 1008 UVD_LMI_CTRL__REQ_MODE_MASK | 1009 0x00100000L); 1010 1011#ifdef __BIG_ENDIAN 1012 /* swap (8 in 32) RB and IB */ 1013 lmi_swap_cntl = 0xa; 1014 mp_swap_cntl = 0; 1015#endif 1016 WREG32_SOC15(UVD, k, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl); 1017 WREG32_SOC15(UVD, k, mmUVD_MP_SWAP_CNTL, mp_swap_cntl); 1018 1019 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXA0, 0x40c2040); 1020 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXA1, 0x0); 1021 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXB0, 0x40c2040); 1022 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXB1, 0x0); 1023 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_ALU, 0); 1024 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUX, 0x88); 1025 1026 /* take all subblocks out of reset, except VCPU */ 1027 WREG32_SOC15(UVD, k, mmUVD_SOFT_RESET, 1028 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 1029 mdelay(5); 1030 1031 /* enable VCPU clock */ 1032 WREG32_SOC15(UVD, k, mmUVD_VCPU_CNTL, 1033 UVD_VCPU_CNTL__CLK_EN_MASK); 1034 1035 /* enable UMC */ 1036 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_LMI_CTRL2), 0, 1037 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 1038 1039 /* boot up the VCPU */ 1040 WREG32_SOC15(UVD, k, mmUVD_SOFT_RESET, 0); 1041 mdelay(10); 1042 1043 for (i = 0; i < 10; ++i) { 1044 uint32_t status; 1045 1046 for (j = 0; j < 100; ++j) { 1047 status = RREG32_SOC15(UVD, k, mmUVD_STATUS); 1048 if (status & 2) 1049 break; 1050 mdelay(10); 1051 } 1052 r = 0; 1053 if (status & 2) 1054 break; 1055 1056 DRM_ERROR("UVD(%d) not responding, trying to reset the VCPU!!!\n", k); 1057 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_SOFT_RESET), 1058 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, 1059 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 1060 mdelay(10); 1061 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_SOFT_RESET), 0, 1062 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 1063 mdelay(10); 1064 r = -1; 1065 } 1066 1067 if (r) { 1068 DRM_ERROR("UVD(%d) not responding, giving up!!!\n", k); 1069 return r; 1070 } 1071 /* enable master interrupt */ 1072 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_MASTINT_EN), 1073 (UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK), 1074 ~(UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK)); 1075 1076 /* clear the bit 4 of UVD_STATUS */ 1077 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_STATUS), 0, 1078 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); 1079 1080 /* force RBC into idle state */ 1081 rb_bufsz = order_base_2(ring->ring_size); 1082 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 1083 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1084 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 1085 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0); 1086 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1087 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 1088 WREG32_SOC15(UVD, k, mmUVD_RBC_RB_CNTL, tmp); 1089 1090 /* set the write pointer delay */ 1091 WREG32_SOC15(UVD, k, mmUVD_RBC_RB_WPTR_CNTL, 0); 1092 1093 /* set the wb address */ 1094 WREG32_SOC15(UVD, k, mmUVD_RBC_RB_RPTR_ADDR, 1095 (upper_32_bits(ring->gpu_addr) >> 2)); 1096 1097 /* program the RB_BASE for ring buffer */ 1098 WREG32_SOC15(UVD, k, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 1099 lower_32_bits(ring->gpu_addr)); 1100 WREG32_SOC15(UVD, k, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 1101 upper_32_bits(ring->gpu_addr)); 1102 1103 /* Initialize the ring buffer's read and write pointers */ 1104 WREG32_SOC15(UVD, k, mmUVD_RBC_RB_RPTR, 0); 1105 1106 ring->wptr = RREG32_SOC15(UVD, k, mmUVD_RBC_RB_RPTR); 1107 WREG32_SOC15(UVD, k, mmUVD_RBC_RB_WPTR, 1108 lower_32_bits(ring->wptr)); 1109 1110 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_RBC_RB_CNTL), 0, 1111 ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK); 1112 1113 ring = &adev->uvd.inst[k].ring_enc[0]; 1114 WREG32_SOC15(UVD, k, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); 1115 WREG32_SOC15(UVD, k, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1116 WREG32_SOC15(UVD, k, mmUVD_RB_BASE_LO, ring->gpu_addr); 1117 WREG32_SOC15(UVD, k, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1118 WREG32_SOC15(UVD, k, mmUVD_RB_SIZE, ring->ring_size / 4); 1119 1120 ring = &adev->uvd.inst[k].ring_enc[1]; 1121 WREG32_SOC15(UVD, k, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); 1122 WREG32_SOC15(UVD, k, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 1123 WREG32_SOC15(UVD, k, mmUVD_RB_BASE_LO2, ring->gpu_addr); 1124 WREG32_SOC15(UVD, k, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 1125 WREG32_SOC15(UVD, k, mmUVD_RB_SIZE2, ring->ring_size / 4); 1126 } 1127 return 0; 1128} 1129 1130/** 1131 * uvd_v7_0_stop - stop UVD block 1132 * 1133 * @adev: amdgpu_device pointer 1134 * 1135 * stop the UVD block 1136 */ 1137static void uvd_v7_0_stop(struct amdgpu_device *adev) 1138{ 1139 uint8_t i = 0; 1140 1141 for (i = 0; i < adev->uvd.num_uvd_inst; ++i) { 1142 if (adev->uvd.harvest_config & (1 << i)) 1143 continue; 1144 /* force RBC into idle state */ 1145 WREG32_SOC15(UVD, i, mmUVD_RBC_RB_CNTL, 0x11010101); 1146 1147 /* Stall UMC and register bus before resetting VCPU */ 1148 WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2), 1149 UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, 1150 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 1151 mdelay(1); 1152 1153 /* put VCPU into reset */ 1154 WREG32_SOC15(UVD, i, mmUVD_SOFT_RESET, 1155 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 1156 mdelay(5); 1157 1158 /* disable VCPU clock */ 1159 WREG32_SOC15(UVD, i, mmUVD_VCPU_CNTL, 0x0); 1160 1161 /* Unstall UMC and register bus */ 1162 WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2), 0, 1163 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 1164 } 1165} 1166 1167/** 1168 * uvd_v7_0_ring_emit_fence - emit an fence & trap command 1169 * 1170 * @ring: amdgpu_ring pointer 1171 * @addr: address 1172 * @seq: sequence number 1173 * @flags: fence related flags 1174 * 1175 * Write a fence and a trap command to the ring. 1176 */ 1177static void uvd_v7_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 1178 unsigned flags) 1179{ 1180 struct amdgpu_device *adev = ring->adev; 1181 1182 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 1183 1184 amdgpu_ring_write(ring, 1185 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_CONTEXT_ID), 0)); 1186 amdgpu_ring_write(ring, seq); 1187 amdgpu_ring_write(ring, 1188 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0)); 1189 amdgpu_ring_write(ring, addr & 0xffffffff); 1190 amdgpu_ring_write(ring, 1191 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0)); 1192 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff); 1193 amdgpu_ring_write(ring, 1194 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0)); 1195 amdgpu_ring_write(ring, 0); 1196 1197 amdgpu_ring_write(ring, 1198 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0)); 1199 amdgpu_ring_write(ring, 0); 1200 amdgpu_ring_write(ring, 1201 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0)); 1202 amdgpu_ring_write(ring, 0); 1203 amdgpu_ring_write(ring, 1204 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0)); 1205 amdgpu_ring_write(ring, 2); 1206} 1207 1208/** 1209 * uvd_v7_0_enc_ring_emit_fence - emit an enc fence & trap command 1210 * 1211 * @ring: amdgpu_ring pointer 1212 * @addr: address 1213 * @seq: sequence number 1214 * @flags: fence related flags 1215 * 1216 * Write enc a fence and a trap command to the ring. 1217 */ 1218static void uvd_v7_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 1219 u64 seq, unsigned flags) 1220{ 1221 1222 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 1223 1224 amdgpu_ring_write(ring, HEVC_ENC_CMD_FENCE); 1225 amdgpu_ring_write(ring, addr); 1226 amdgpu_ring_write(ring, upper_32_bits(addr)); 1227 amdgpu_ring_write(ring, seq); 1228 amdgpu_ring_write(ring, HEVC_ENC_CMD_TRAP); 1229} 1230 1231/** 1232 * uvd_v7_0_ring_emit_hdp_flush - skip HDP flushing 1233 * 1234 * @ring: amdgpu_ring pointer 1235 */ 1236static void uvd_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 1237{ 1238 /* The firmware doesn't seem to like touching registers at this point. */ 1239} 1240 1241/** 1242 * uvd_v7_0_ring_test_ring - register write test 1243 * 1244 * @ring: amdgpu_ring pointer 1245 * 1246 * Test if we can successfully write to the context register 1247 */ 1248static int uvd_v7_0_ring_test_ring(struct amdgpu_ring *ring) 1249{ 1250 struct amdgpu_device *adev = ring->adev; 1251 uint32_t tmp = 0; 1252 unsigned i; 1253 int r; 1254 1255 WREG32_SOC15(UVD, ring->me, mmUVD_CONTEXT_ID, 0xCAFEDEAD); 1256 r = amdgpu_ring_alloc(ring, 3); 1257 if (r) 1258 return r; 1259 1260 amdgpu_ring_write(ring, 1261 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_CONTEXT_ID), 0)); 1262 amdgpu_ring_write(ring, 0xDEADBEEF); 1263 amdgpu_ring_commit(ring); 1264 for (i = 0; i < adev->usec_timeout; i++) { 1265 tmp = RREG32_SOC15(UVD, ring->me, mmUVD_CONTEXT_ID); 1266 if (tmp == 0xDEADBEEF) 1267 break; 1268 udelay(1); 1269 } 1270 1271 if (i >= adev->usec_timeout) 1272 r = -ETIMEDOUT; 1273 1274 return r; 1275} 1276 1277/** 1278 * uvd_v7_0_ring_patch_cs_in_place - Patch the IB for command submission. 1279 * 1280 * @p: the CS parser with the IBs 1281 * @job: which job this ib is in 1282 * @ib: which IB to patch 1283 * 1284 */ 1285static int uvd_v7_0_ring_patch_cs_in_place(struct amdgpu_cs_parser *p, 1286 struct amdgpu_job *job, 1287 struct amdgpu_ib *ib) 1288{ 1289 struct amdgpu_ring *ring = to_amdgpu_ring(job->base.sched); 1290 unsigned i; 1291 1292 /* No patching necessary for the first instance */ 1293 if (!ring->me) 1294 return 0; 1295 1296 for (i = 0; i < ib->length_dw; i += 2) { 1297 uint32_t reg = amdgpu_ib_get_value(ib, i); 1298 1299 reg -= p->adev->reg_offset[UVD_HWIP][0][1]; 1300 reg += p->adev->reg_offset[UVD_HWIP][1][1]; 1301 1302 amdgpu_ib_set_value(ib, i, reg); 1303 } 1304 return 0; 1305} 1306 1307/** 1308 * uvd_v7_0_ring_emit_ib - execute indirect buffer 1309 * 1310 * @ring: amdgpu_ring pointer 1311 * @job: job to retrieve vmid from 1312 * @ib: indirect buffer to execute 1313 * @flags: unused 1314 * 1315 * Write ring commands to execute the indirect buffer 1316 */ 1317static void uvd_v7_0_ring_emit_ib(struct amdgpu_ring *ring, 1318 struct amdgpu_job *job, 1319 struct amdgpu_ib *ib, 1320 uint32_t flags) 1321{ 1322 struct amdgpu_device *adev = ring->adev; 1323 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 1324 1325 amdgpu_ring_write(ring, 1326 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_LMI_RBC_IB_VMID), 0)); 1327 amdgpu_ring_write(ring, vmid); 1328 1329 amdgpu_ring_write(ring, 1330 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_LMI_RBC_IB_64BIT_BAR_LOW), 0)); 1331 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 1332 amdgpu_ring_write(ring, 1333 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH), 0)); 1334 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 1335 amdgpu_ring_write(ring, 1336 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_RBC_IB_SIZE), 0)); 1337 amdgpu_ring_write(ring, ib->length_dw); 1338} 1339 1340/** 1341 * uvd_v7_0_enc_ring_emit_ib - enc execute indirect buffer 1342 * 1343 * @ring: amdgpu_ring pointer 1344 * @job: job to retrive vmid from 1345 * @ib: indirect buffer to execute 1346 * @flags: unused 1347 * 1348 * Write enc ring commands to execute the indirect buffer 1349 */ 1350static void uvd_v7_0_enc_ring_emit_ib(struct amdgpu_ring *ring, 1351 struct amdgpu_job *job, 1352 struct amdgpu_ib *ib, 1353 uint32_t flags) 1354{ 1355 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 1356 1357 amdgpu_ring_write(ring, HEVC_ENC_CMD_IB_VM); 1358 amdgpu_ring_write(ring, vmid); 1359 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 1360 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 1361 amdgpu_ring_write(ring, ib->length_dw); 1362} 1363 1364static void uvd_v7_0_ring_emit_wreg(struct amdgpu_ring *ring, 1365 uint32_t reg, uint32_t val) 1366{ 1367 struct amdgpu_device *adev = ring->adev; 1368 1369 amdgpu_ring_write(ring, 1370 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0)); 1371 amdgpu_ring_write(ring, reg << 2); 1372 amdgpu_ring_write(ring, 1373 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0)); 1374 amdgpu_ring_write(ring, val); 1375 amdgpu_ring_write(ring, 1376 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0)); 1377 amdgpu_ring_write(ring, 8); 1378} 1379 1380static void uvd_v7_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1381 uint32_t val, uint32_t mask) 1382{ 1383 struct amdgpu_device *adev = ring->adev; 1384 1385 amdgpu_ring_write(ring, 1386 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0)); 1387 amdgpu_ring_write(ring, reg << 2); 1388 amdgpu_ring_write(ring, 1389 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0)); 1390 amdgpu_ring_write(ring, val); 1391 amdgpu_ring_write(ring, 1392 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GP_SCRATCH8), 0)); 1393 amdgpu_ring_write(ring, mask); 1394 amdgpu_ring_write(ring, 1395 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0)); 1396 amdgpu_ring_write(ring, 12); 1397} 1398 1399static void uvd_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 1400 unsigned vmid, uint64_t pd_addr) 1401{ 1402 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub]; 1403 uint32_t data0, data1, mask; 1404 1405 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1406 1407 /* wait for reg writes */ 1408 data0 = hub->ctx0_ptb_addr_lo32 + vmid * hub->ctx_addr_distance; 1409 data1 = lower_32_bits(pd_addr); 1410 mask = 0xffffffff; 1411 uvd_v7_0_ring_emit_reg_wait(ring, data0, data1, mask); 1412} 1413 1414static void uvd_v7_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 1415{ 1416 struct amdgpu_device *adev = ring->adev; 1417 int i; 1418 1419 WARN_ON(ring->wptr % 2 || count % 2); 1420 1421 for (i = 0; i < count / 2; i++) { 1422 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_NO_OP), 0)); 1423 amdgpu_ring_write(ring, 0); 1424 } 1425} 1426 1427static void uvd_v7_0_enc_ring_insert_end(struct amdgpu_ring *ring) 1428{ 1429 amdgpu_ring_write(ring, HEVC_ENC_CMD_END); 1430} 1431 1432static void uvd_v7_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring, 1433 uint32_t reg, uint32_t val, 1434 uint32_t mask) 1435{ 1436 amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WAIT); 1437 amdgpu_ring_write(ring, reg << 2); 1438 amdgpu_ring_write(ring, mask); 1439 amdgpu_ring_write(ring, val); 1440} 1441 1442static void uvd_v7_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring, 1443 unsigned int vmid, uint64_t pd_addr) 1444{ 1445 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub]; 1446 1447 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1448 1449 /* wait for reg writes */ 1450 uvd_v7_0_enc_ring_emit_reg_wait(ring, hub->ctx0_ptb_addr_lo32 + 1451 vmid * hub->ctx_addr_distance, 1452 lower_32_bits(pd_addr), 0xffffffff); 1453} 1454 1455static void uvd_v7_0_enc_ring_emit_wreg(struct amdgpu_ring *ring, 1456 uint32_t reg, uint32_t val) 1457{ 1458 amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WRITE); 1459 amdgpu_ring_write(ring, reg << 2); 1460 amdgpu_ring_write(ring, val); 1461} 1462 1463#if 0 1464static bool uvd_v7_0_is_idle(void *handle) 1465{ 1466 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1467 1468 return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK); 1469} 1470 1471static int uvd_v7_0_wait_for_idle(void *handle) 1472{ 1473 unsigned i; 1474 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1475 1476 for (i = 0; i < adev->usec_timeout; i++) { 1477 if (uvd_v7_0_is_idle(handle)) 1478 return 0; 1479 } 1480 return -ETIMEDOUT; 1481} 1482 1483#define AMDGPU_UVD_STATUS_BUSY_MASK 0xfd 1484static bool uvd_v7_0_check_soft_reset(void *handle) 1485{ 1486 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1487 u32 srbm_soft_reset = 0; 1488 u32 tmp = RREG32(mmSRBM_STATUS); 1489 1490 if (REG_GET_FIELD(tmp, SRBM_STATUS, UVD_RQ_PENDING) || 1491 REG_GET_FIELD(tmp, SRBM_STATUS, UVD_BUSY) || 1492 (RREG32_SOC15(UVD, ring->me, mmUVD_STATUS) & 1493 AMDGPU_UVD_STATUS_BUSY_MASK)) 1494 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, 1495 SRBM_SOFT_RESET, SOFT_RESET_UVD, 1); 1496 1497 if (srbm_soft_reset) { 1498 adev->uvd.inst[ring->me].srbm_soft_reset = srbm_soft_reset; 1499 return true; 1500 } else { 1501 adev->uvd.inst[ring->me].srbm_soft_reset = 0; 1502 return false; 1503 } 1504} 1505 1506static int uvd_v7_0_pre_soft_reset(void *handle) 1507{ 1508 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1509 1510 if (!adev->uvd.inst[ring->me].srbm_soft_reset) 1511 return 0; 1512 1513 uvd_v7_0_stop(adev); 1514 return 0; 1515} 1516 1517static int uvd_v7_0_soft_reset(void *handle) 1518{ 1519 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1520 u32 srbm_soft_reset; 1521 1522 if (!adev->uvd.inst[ring->me].srbm_soft_reset) 1523 return 0; 1524 srbm_soft_reset = adev->uvd.inst[ring->me].srbm_soft_reset; 1525 1526 if (srbm_soft_reset) { 1527 u32 tmp; 1528 1529 tmp = RREG32(mmSRBM_SOFT_RESET); 1530 tmp |= srbm_soft_reset; 1531 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 1532 WREG32(mmSRBM_SOFT_RESET, tmp); 1533 tmp = RREG32(mmSRBM_SOFT_RESET); 1534 1535 udelay(50); 1536 1537 tmp &= ~srbm_soft_reset; 1538 WREG32(mmSRBM_SOFT_RESET, tmp); 1539 tmp = RREG32(mmSRBM_SOFT_RESET); 1540 1541 /* Wait a little for things to settle down */ 1542 udelay(50); 1543 } 1544 1545 return 0; 1546} 1547 1548static int uvd_v7_0_post_soft_reset(void *handle) 1549{ 1550 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1551 1552 if (!adev->uvd.inst[ring->me].srbm_soft_reset) 1553 return 0; 1554 1555 mdelay(5); 1556 1557 return uvd_v7_0_start(adev); 1558} 1559#endif 1560 1561static int uvd_v7_0_set_interrupt_state(struct amdgpu_device *adev, 1562 struct amdgpu_irq_src *source, 1563 unsigned type, 1564 enum amdgpu_interrupt_state state) 1565{ 1566 // TODO 1567 return 0; 1568} 1569 1570static int uvd_v7_0_process_interrupt(struct amdgpu_device *adev, 1571 struct amdgpu_irq_src *source, 1572 struct amdgpu_iv_entry *entry) 1573{ 1574 uint32_t ip_instance; 1575 1576 switch (entry->client_id) { 1577 case SOC15_IH_CLIENTID_UVD: 1578 ip_instance = 0; 1579 break; 1580 case SOC15_IH_CLIENTID_UVD1: 1581 ip_instance = 1; 1582 break; 1583 default: 1584 DRM_ERROR("Unhandled client id: %d\n", entry->client_id); 1585 return 0; 1586 } 1587 1588 DRM_DEBUG("IH: UVD TRAP\n"); 1589 1590 switch (entry->src_id) { 1591 case 124: 1592 amdgpu_fence_process(&adev->uvd.inst[ip_instance].ring); 1593 break; 1594 case 119: 1595 amdgpu_fence_process(&adev->uvd.inst[ip_instance].ring_enc[0]); 1596 break; 1597 case 120: 1598 if (!amdgpu_sriov_vf(adev)) 1599 amdgpu_fence_process(&adev->uvd.inst[ip_instance].ring_enc[1]); 1600 break; 1601 default: 1602 DRM_ERROR("Unhandled interrupt: %d %d\n", 1603 entry->src_id, entry->src_data[0]); 1604 break; 1605 } 1606 1607 return 0; 1608} 1609 1610#if 0 1611static void uvd_v7_0_set_sw_clock_gating(struct amdgpu_device *adev) 1612{ 1613 uint32_t data, data1, data2, suvd_flags; 1614 1615 data = RREG32_SOC15(UVD, ring->me, mmUVD_CGC_CTRL); 1616 data1 = RREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE); 1617 data2 = RREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_CTRL); 1618 1619 data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK | 1620 UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK); 1621 1622 suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK | 1623 UVD_SUVD_CGC_GATE__SIT_MASK | 1624 UVD_SUVD_CGC_GATE__SMP_MASK | 1625 UVD_SUVD_CGC_GATE__SCM_MASK | 1626 UVD_SUVD_CGC_GATE__SDB_MASK; 1627 1628 data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK | 1629 (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) | 1630 (4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY)); 1631 1632 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | 1633 UVD_CGC_CTRL__UDEC_CM_MODE_MASK | 1634 UVD_CGC_CTRL__UDEC_IT_MODE_MASK | 1635 UVD_CGC_CTRL__UDEC_DB_MODE_MASK | 1636 UVD_CGC_CTRL__UDEC_MP_MODE_MASK | 1637 UVD_CGC_CTRL__SYS_MODE_MASK | 1638 UVD_CGC_CTRL__UDEC_MODE_MASK | 1639 UVD_CGC_CTRL__MPEG2_MODE_MASK | 1640 UVD_CGC_CTRL__REGS_MODE_MASK | 1641 UVD_CGC_CTRL__RBC_MODE_MASK | 1642 UVD_CGC_CTRL__LMI_MC_MODE_MASK | 1643 UVD_CGC_CTRL__LMI_UMC_MODE_MASK | 1644 UVD_CGC_CTRL__IDCT_MODE_MASK | 1645 UVD_CGC_CTRL__MPRD_MODE_MASK | 1646 UVD_CGC_CTRL__MPC_MODE_MASK | 1647 UVD_CGC_CTRL__LBSI_MODE_MASK | 1648 UVD_CGC_CTRL__LRBBM_MODE_MASK | 1649 UVD_CGC_CTRL__WCB_MODE_MASK | 1650 UVD_CGC_CTRL__VCPU_MODE_MASK | 1651 UVD_CGC_CTRL__JPEG_MODE_MASK | 1652 UVD_CGC_CTRL__JPEG2_MODE_MASK | 1653 UVD_CGC_CTRL__SCPU_MODE_MASK); 1654 data2 &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK | 1655 UVD_SUVD_CGC_CTRL__SIT_MODE_MASK | 1656 UVD_SUVD_CGC_CTRL__SMP_MODE_MASK | 1657 UVD_SUVD_CGC_CTRL__SCM_MODE_MASK | 1658 UVD_SUVD_CGC_CTRL__SDB_MODE_MASK); 1659 data1 |= suvd_flags; 1660 1661 WREG32_SOC15(UVD, ring->me, mmUVD_CGC_CTRL, data); 1662 WREG32_SOC15(UVD, ring->me, mmUVD_CGC_GATE, 0); 1663 WREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE, data1); 1664 WREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_CTRL, data2); 1665} 1666 1667static void uvd_v7_0_set_hw_clock_gating(struct amdgpu_device *adev) 1668{ 1669 uint32_t data, data1, cgc_flags, suvd_flags; 1670 1671 data = RREG32_SOC15(UVD, ring->me, mmUVD_CGC_GATE); 1672 data1 = RREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE); 1673 1674 cgc_flags = UVD_CGC_GATE__SYS_MASK | 1675 UVD_CGC_GATE__UDEC_MASK | 1676 UVD_CGC_GATE__MPEG2_MASK | 1677 UVD_CGC_GATE__RBC_MASK | 1678 UVD_CGC_GATE__LMI_MC_MASK | 1679 UVD_CGC_GATE__IDCT_MASK | 1680 UVD_CGC_GATE__MPRD_MASK | 1681 UVD_CGC_GATE__MPC_MASK | 1682 UVD_CGC_GATE__LBSI_MASK | 1683 UVD_CGC_GATE__LRBBM_MASK | 1684 UVD_CGC_GATE__UDEC_RE_MASK | 1685 UVD_CGC_GATE__UDEC_CM_MASK | 1686 UVD_CGC_GATE__UDEC_IT_MASK | 1687 UVD_CGC_GATE__UDEC_DB_MASK | 1688 UVD_CGC_GATE__UDEC_MP_MASK | 1689 UVD_CGC_GATE__WCB_MASK | 1690 UVD_CGC_GATE__VCPU_MASK | 1691 UVD_CGC_GATE__SCPU_MASK | 1692 UVD_CGC_GATE__JPEG_MASK | 1693 UVD_CGC_GATE__JPEG2_MASK; 1694 1695 suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK | 1696 UVD_SUVD_CGC_GATE__SIT_MASK | 1697 UVD_SUVD_CGC_GATE__SMP_MASK | 1698 UVD_SUVD_CGC_GATE__SCM_MASK | 1699 UVD_SUVD_CGC_GATE__SDB_MASK; 1700 1701 data |= cgc_flags; 1702 data1 |= suvd_flags; 1703 1704 WREG32_SOC15(UVD, ring->me, mmUVD_CGC_GATE, data); 1705 WREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE, data1); 1706} 1707 1708static void uvd_v7_0_set_bypass_mode(struct amdgpu_device *adev, bool enable) 1709{ 1710 u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL); 1711 1712 if (enable) 1713 tmp |= (GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK | 1714 GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK); 1715 else 1716 tmp &= ~(GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK | 1717 GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK); 1718 1719 WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp); 1720} 1721 1722 1723static int uvd_v7_0_set_clockgating_state(void *handle, 1724 enum amd_clockgating_state state) 1725{ 1726 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1727 bool enable = (state == AMD_CG_STATE_GATE); 1728 1729 uvd_v7_0_set_bypass_mode(adev, enable); 1730 1731 if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) 1732 return 0; 1733 1734 if (enable) { 1735 /* disable HW gating and enable Sw gating */ 1736 uvd_v7_0_set_sw_clock_gating(adev); 1737 } else { 1738 /* wait for STATUS to clear */ 1739 if (uvd_v7_0_wait_for_idle(handle)) 1740 return -EBUSY; 1741 1742 /* enable HW gates because UVD is idle */ 1743 /* uvd_v7_0_set_hw_clock_gating(adev); */ 1744 } 1745 1746 return 0; 1747} 1748 1749static int uvd_v7_0_set_powergating_state(void *handle, 1750 enum amd_powergating_state state) 1751{ 1752 /* This doesn't actually powergate the UVD block. 1753 * That's done in the dpm code via the SMC. This 1754 * just re-inits the block as necessary. The actual 1755 * gating still happens in the dpm code. We should 1756 * revisit this when there is a cleaner line between 1757 * the smc and the hw blocks 1758 */ 1759 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1760 1761 if (!(adev->pg_flags & AMD_PG_SUPPORT_UVD)) 1762 return 0; 1763 1764 WREG32_SOC15(UVD, ring->me, mmUVD_POWER_STATUS, UVD_POWER_STATUS__UVD_PG_EN_MASK); 1765 1766 if (state == AMD_PG_STATE_GATE) { 1767 uvd_v7_0_stop(adev); 1768 return 0; 1769 } else { 1770 return uvd_v7_0_start(adev); 1771 } 1772} 1773#endif 1774 1775static int uvd_v7_0_set_clockgating_state(void *handle, 1776 enum amd_clockgating_state state) 1777{ 1778 /* needed for driver unload*/ 1779 return 0; 1780} 1781 1782const struct amd_ip_funcs uvd_v7_0_ip_funcs = { 1783 .name = "uvd_v7_0", 1784 .early_init = uvd_v7_0_early_init, 1785 .late_init = NULL, 1786 .sw_init = uvd_v7_0_sw_init, 1787 .sw_fini = uvd_v7_0_sw_fini, 1788 .hw_init = uvd_v7_0_hw_init, 1789 .hw_fini = uvd_v7_0_hw_fini, 1790 .suspend = uvd_v7_0_suspend, 1791 .resume = uvd_v7_0_resume, 1792 .is_idle = NULL /* uvd_v7_0_is_idle */, 1793 .wait_for_idle = NULL /* uvd_v7_0_wait_for_idle */, 1794 .check_soft_reset = NULL /* uvd_v7_0_check_soft_reset */, 1795 .pre_soft_reset = NULL /* uvd_v7_0_pre_soft_reset */, 1796 .soft_reset = NULL /* uvd_v7_0_soft_reset */, 1797 .post_soft_reset = NULL /* uvd_v7_0_post_soft_reset */, 1798 .set_clockgating_state = uvd_v7_0_set_clockgating_state, 1799 .set_powergating_state = NULL /* uvd_v7_0_set_powergating_state */, 1800}; 1801 1802static const struct amdgpu_ring_funcs uvd_v7_0_ring_vm_funcs = { 1803 .type = AMDGPU_RING_TYPE_UVD, 1804 .align_mask = 0xf, 1805 .support_64bit_ptrs = false, 1806 .no_user_fence = true, 1807 .get_rptr = uvd_v7_0_ring_get_rptr, 1808 .get_wptr = uvd_v7_0_ring_get_wptr, 1809 .set_wptr = uvd_v7_0_ring_set_wptr, 1810 .patch_cs_in_place = uvd_v7_0_ring_patch_cs_in_place, 1811 .emit_frame_size = 1812 6 + /* hdp invalidate */ 1813 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 1814 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 1815 8 + /* uvd_v7_0_ring_emit_vm_flush */ 1816 14 + 14, /* uvd_v7_0_ring_emit_fence x2 vm fence */ 1817 .emit_ib_size = 8, /* uvd_v7_0_ring_emit_ib */ 1818 .emit_ib = uvd_v7_0_ring_emit_ib, 1819 .emit_fence = uvd_v7_0_ring_emit_fence, 1820 .emit_vm_flush = uvd_v7_0_ring_emit_vm_flush, 1821 .emit_hdp_flush = uvd_v7_0_ring_emit_hdp_flush, 1822 .test_ring = uvd_v7_0_ring_test_ring, 1823 .test_ib = amdgpu_uvd_ring_test_ib, 1824 .insert_nop = uvd_v7_0_ring_insert_nop, 1825 .pad_ib = amdgpu_ring_generic_pad_ib, 1826 .begin_use = amdgpu_uvd_ring_begin_use, 1827 .end_use = amdgpu_uvd_ring_end_use, 1828 .emit_wreg = uvd_v7_0_ring_emit_wreg, 1829 .emit_reg_wait = uvd_v7_0_ring_emit_reg_wait, 1830 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1831}; 1832 1833static const struct amdgpu_ring_funcs uvd_v7_0_enc_ring_vm_funcs = { 1834 .type = AMDGPU_RING_TYPE_UVD_ENC, 1835 .align_mask = 0x3f, 1836 .nop = HEVC_ENC_CMD_NO_OP, 1837 .support_64bit_ptrs = false, 1838 .no_user_fence = true, 1839 .get_rptr = uvd_v7_0_enc_ring_get_rptr, 1840 .get_wptr = uvd_v7_0_enc_ring_get_wptr, 1841 .set_wptr = uvd_v7_0_enc_ring_set_wptr, 1842 .emit_frame_size = 1843 3 + 3 + /* hdp flush / invalidate */ 1844 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1845 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 1846 4 + /* uvd_v7_0_enc_ring_emit_vm_flush */ 1847 5 + 5 + /* uvd_v7_0_enc_ring_emit_fence x2 vm fence */ 1848 1, /* uvd_v7_0_enc_ring_insert_end */ 1849 .emit_ib_size = 5, /* uvd_v7_0_enc_ring_emit_ib */ 1850 .emit_ib = uvd_v7_0_enc_ring_emit_ib, 1851 .emit_fence = uvd_v7_0_enc_ring_emit_fence, 1852 .emit_vm_flush = uvd_v7_0_enc_ring_emit_vm_flush, 1853 .test_ring = uvd_v7_0_enc_ring_test_ring, 1854 .test_ib = uvd_v7_0_enc_ring_test_ib, 1855 .insert_nop = amdgpu_ring_insert_nop, 1856 .insert_end = uvd_v7_0_enc_ring_insert_end, 1857 .pad_ib = amdgpu_ring_generic_pad_ib, 1858 .begin_use = amdgpu_uvd_ring_begin_use, 1859 .end_use = amdgpu_uvd_ring_end_use, 1860 .emit_wreg = uvd_v7_0_enc_ring_emit_wreg, 1861 .emit_reg_wait = uvd_v7_0_enc_ring_emit_reg_wait, 1862 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1863}; 1864 1865static void uvd_v7_0_set_ring_funcs(struct amdgpu_device *adev) 1866{ 1867 int i; 1868 1869 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 1870 if (adev->uvd.harvest_config & (1 << i)) 1871 continue; 1872 adev->uvd.inst[i].ring.funcs = &uvd_v7_0_ring_vm_funcs; 1873 adev->uvd.inst[i].ring.me = i; 1874 DRM_INFO("UVD(%d) is enabled in VM mode\n", i); 1875 } 1876} 1877 1878static void uvd_v7_0_set_enc_ring_funcs(struct amdgpu_device *adev) 1879{ 1880 int i, j; 1881 1882 for (j = 0; j < adev->uvd.num_uvd_inst; j++) { 1883 if (adev->uvd.harvest_config & (1 << j)) 1884 continue; 1885 for (i = 0; i < adev->uvd.num_enc_rings; ++i) { 1886 adev->uvd.inst[j].ring_enc[i].funcs = &uvd_v7_0_enc_ring_vm_funcs; 1887 adev->uvd.inst[j].ring_enc[i].me = j; 1888 } 1889 1890 DRM_INFO("UVD(%d) ENC is enabled in VM mode\n", j); 1891 } 1892} 1893 1894static const struct amdgpu_irq_src_funcs uvd_v7_0_irq_funcs = { 1895 .set = uvd_v7_0_set_interrupt_state, 1896 .process = uvd_v7_0_process_interrupt, 1897}; 1898 1899static void uvd_v7_0_set_irq_funcs(struct amdgpu_device *adev) 1900{ 1901 int i; 1902 1903 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 1904 if (adev->uvd.harvest_config & (1 << i)) 1905 continue; 1906 adev->uvd.inst[i].irq.num_types = adev->uvd.num_enc_rings + 1; 1907 adev->uvd.inst[i].irq.funcs = &uvd_v7_0_irq_funcs; 1908 } 1909} 1910 1911const struct amdgpu_ip_block_version uvd_v7_0_ip_block = { 1912 .type = AMD_IP_BLOCK_TYPE_UVD, 1913 .major = 7, 1914 .minor = 0, 1915 .rev = 0, 1916 .funcs = &uvd_v7_0_ip_funcs, 1917}; 1918