amd/amdgpu/sdma_v5_2.c

96 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE));
97 	amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
98 	amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
99 	amdgpu_ring_write(ring, 1);
101 	amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */
213 			amdgpu_ring_write(ring, ring->funcs->nop |
216 			amdgpu_ring_write(ring, ring->funcs->nop);
247 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
250 	amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
251 	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
252 	amdgpu_ring_write(ring, ib->length_dw);
253 	amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr));
254 	amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr));
272 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_GCR_REQ));
273 	amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(0));
274 	amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(gcr_cntl) |
276 	amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(0) |
278 	amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(0) |
300 		amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
303 		amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2);
304 		amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2);
305 		amdgpu_ring_write(ring, ref_and_mask); /* reference */
306 		amdgpu_ring_write(ring, ref_and_mask); /* mask */
307 		amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
329 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
333 	amdgpu_ring_write(ring, lower_32_bits(addr));
334 	amdgpu_ring_write(ring, upper_32_bits(addr));
335 	amdgpu_ring_write(ring, lower_32_bits(seq));
340 		amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
344 		amdgpu_ring_write(ring, lower_32_bits(addr));
345 		amdgpu_ring_write(ring, upper_32_bits(addr));
346 		amdgpu_ring_write(ring, upper_32_bits(seq));
353 		amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
354 		amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(ctx));
863 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
865 	amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
866 	amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
867 	amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
868 	amdgpu_ring_write(ring, 0xDEADBEEF);
1114 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1118 	amdgpu_ring_write(ring, addr & 0xfffffffc);
1119 	amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1120 	amdgpu_ring_write(ring, seq); /* reference */
1121 	amdgpu_ring_write(ring, 0xffffffff); /* mask */
1122 	amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1146 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1148 	amdgpu_ring_write(ring, reg);
1149 	amdgpu_ring_write(ring, val);
1155 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1158 	amdgpu_ring_write(ring, reg << 2);
1159 	amdgpu_ring_write(ring, 0);
1160 	amdgpu_ring_write(ring, val); /* reference */
1161 	amdgpu_ring_write(ring, mask); /* mask */
1162 	amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |