Lines Matching refs:amdgpu_ring_write
72 amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0));
73 amdgpu_ring_write(ring, DMA_IB_PACKET(DMA_PACKET_INDIRECT_BUFFER, vmid, 0));
74 amdgpu_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0));
75 amdgpu_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF));
97 amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0, 0, 0));
98 amdgpu_ring_write(ring, addr & 0xfffffffc);
99 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xff));
100 amdgpu_ring_write(ring, seq);
104 amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0, 0, 0));
105 amdgpu_ring_write(ring, addr & 0xfffffffc);
106 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xff));
107 amdgpu_ring_write(ring, upper_32_bits(seq));
110 amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_TRAP, 0, 0, 0, 0));
218 amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 0, 1));
219 amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
220 amdgpu_ring_write(ring, upper_32_bits(gpu_addr) & 0xff);
221 amdgpu_ring_write(ring, 0xDEADBEEF);
424 amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_POLL_REG_MEM, 0, 0, 0, 0) |
426 amdgpu_ring_write(ring, lower_32_bits(addr));
427 amdgpu_ring_write(ring, (0xff << 16) | upper_32_bits(addr)); /* retry, addr_hi */
428 amdgpu_ring_write(ring, 0xffffffff); /* mask */
429 amdgpu_ring_write(ring, seq); /* value */
430 amdgpu_ring_write(ring, (3 << 28) | 0x20); /* func(equal) | poll interval */
449 amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_POLL_REG_MEM, 0, 0, 0, 0));
450 amdgpu_ring_write(ring, VM_INVALIDATE_REQUEST);
451 amdgpu_ring_write(ring, 0xff << 16); /* retry */
452 amdgpu_ring_write(ring, 1 << vmid); /* mask */
453 amdgpu_ring_write(ring, 0); /* value */
454 amdgpu_ring_write(ring, (0 << 28) | 0x20); /* func(always) | poll interval */
460 amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0));
461 amdgpu_ring_write(ring, (0xf << 16) | reg);
462 amdgpu_ring_write(ring, val);