amd/amdgpu/amdgpu_cik_sdma.c

204 			amdgpu_ring_write(ring, ring->funcs->nop |
207 			amdgpu_ring_write(ring, ring->funcs->nop);
231 	amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_INDIRECT_BUFFER, 0, extra_bits));
232 	amdgpu_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */
233 	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xffffffff);
234 	amdgpu_ring_write(ring, ib->length_dw);
256 	amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits));
257 	amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2);
258 	amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2);
259 	amdgpu_ring_write(ring, ref_and_mask); /* reference */
260 	amdgpu_ring_write(ring, ref_and_mask); /* mask */
261 	amdgpu_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */
281 	amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0));
282 	amdgpu_ring_write(ring, lower_32_bits(addr));
283 	amdgpu_ring_write(ring, upper_32_bits(addr));
284 	amdgpu_ring_write(ring, lower_32_bits(seq));
289 		amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0));
290 		amdgpu_ring_write(ring, lower_32_bits(addr));
291 		amdgpu_ring_write(ring, upper_32_bits(addr));
292 		amdgpu_ring_write(ring, upper_32_bits(seq));
296 	amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_TRAP, 0, 0));
624 	amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0));
625 	amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
626 	amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
627 	amdgpu_ring_write(ring, 1); /* number of DWs to follow */
628 	amdgpu_ring_write(ring, 0xDEADBEEF);
831 	amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0,
835 	amdgpu_ring_write(ring, addr & 0xfffffffc);
836 	amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
837 	amdgpu_ring_write(ring, seq); /* reference */
838 	amdgpu_ring_write(ring, 0xffffffff); /* mask */
839 	amdgpu_ring_write(ring, (0xfff << 16) | 4); /* retry count, poll interval */
860 	amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits));
861 	amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
862 	amdgpu_ring_write(ring, 0);
863 	amdgpu_ring_write(ring, 0); /* reference */
864 	amdgpu_ring_write(ring, 0); /* mask */
865 	amdgpu_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */
871 	amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
872 	amdgpu_ring_write(ring, reg);
873 	amdgpu_ring_write(ring, val);