amd/amdgpu/vcn_v1_0.c

1438 	amdgpu_ring_write(ring,
1440 	amdgpu_ring_write(ring, 0);
1441 	amdgpu_ring_write(ring,
1443 	amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_START << 1);
1457 	amdgpu_ring_write(ring,
1459 	amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_END << 1);
1479 	amdgpu_ring_write(ring,
1481 	amdgpu_ring_write(ring, seq);
1482 	amdgpu_ring_write(ring,
1484 	amdgpu_ring_write(ring, addr & 0xffffffff);
1485 	amdgpu_ring_write(ring,
1487 	amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);
1488 	amdgpu_ring_write(ring,
1490 	amdgpu_ring_write(ring, VCN_DEC_CMD_FENCE << 1);
1492 	amdgpu_ring_write(ring,
1494 	amdgpu_ring_write(ring, 0);
1495 	amdgpu_ring_write(ring,
1497 	amdgpu_ring_write(ring, 0);
1498 	amdgpu_ring_write(ring,
1500 	amdgpu_ring_write(ring, VCN_DEC_CMD_TRAP << 1);
1521 	amdgpu_ring_write(ring,
1523 	amdgpu_ring_write(ring, vmid);
1525 	amdgpu_ring_write(ring,
1527 	amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1528 	amdgpu_ring_write(ring,
1530 	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1531 	amdgpu_ring_write(ring,
1533 	amdgpu_ring_write(ring, ib->length_dw);
1542 	amdgpu_ring_write(ring,
1544 	amdgpu_ring_write(ring, reg << 2);
1545 	amdgpu_ring_write(ring,
1547 	amdgpu_ring_write(ring, val);
1548 	amdgpu_ring_write(ring,
1550 	amdgpu_ring_write(ring, mask);
1551 	amdgpu_ring_write(ring,
1553 	amdgpu_ring_write(ring, VCN_DEC_CMD_REG_READ_COND_WAIT << 1);
1576 	amdgpu_ring_write(ring,
1578 	amdgpu_ring_write(ring, reg << 2);
1579 	amdgpu_ring_write(ring,
1581 	amdgpu_ring_write(ring, val);
1582 	amdgpu_ring_write(ring,
1584 	amdgpu_ring_write(ring, VCN_DEC_CMD_WRITE_REG << 1);
1655 	amdgpu_ring_write(ring, VCN_ENC_CMD_FENCE);
1656 	amdgpu_ring_write(ring, addr);
1657 	amdgpu_ring_write(ring, upper_32_bits(addr));
1658 	amdgpu_ring_write(ring, seq);
1659 	amdgpu_ring_write(ring, VCN_ENC_CMD_TRAP);
1664 	amdgpu_ring_write(ring, VCN_ENC_CMD_END);
1684 	amdgpu_ring_write(ring, VCN_ENC_CMD_IB);
1685 	amdgpu_ring_write(ring, vmid);
1686 	amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1687 	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1688 	amdgpu_ring_write(ring, ib->length_dw);
1695 	amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WAIT);
1696 	amdgpu_ring_write(ring, reg << 2);
1697 	amdgpu_ring_write(ring, mask);
1698 	amdgpu_ring_write(ring, val);
1717 	amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE);
1718 	amdgpu_ring_write(ring,	reg << 2);
1719 	amdgpu_ring_write(ring, val);
1763 		amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP), 0));
1764 		amdgpu_ring_write(ring, 0);