Searched refs:mtdcr (Results 1 - 23 of 23) sorted by relevance

/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/arch/ppc/syslib/
H A Dppc4xx_pic.c45 mtdcr(DCRN_UIC_SR(UIC##n), mask); \
47 mtdcr(DCRN_UIC_ER(UIC##n), ppc_cached_irq_mask[n]); \
53 mtdcr(DCRN_UIC_ER(UIC##n), ppc_cached_irq_mask[n]); \
61 mtdcr(DCRN_UIC_ER(UIC##n), ppc_cached_irq_mask[n]); \
62 mtdcr(DCRN_UIC_SR(UIC##n), mask); \
71 mtdcr(DCRN_UIC_SR(UIC##n), mask); \
76 mtdcr(DCRN_UIC_ER(UIC##n), ppc_cached_irq_mask[n]); \
91 #define ACK_UIC1_PARENT mtdcr(DCRN_UIC_SR(UIC0), UIC0_UIC1NC);
92 #define ACK_UIC2_PARENT mtdcr(DCRN_UIC_SR(UIC0), UIC0_UIC2NC);
93 #define ACK_UIC3_PARENT mtdcr(DCRN_UIC_S
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H A Dppc440spe_pcie.c272 mtdcr(DCRN_PEGPL_REGBAH(PCIE0), 0x0000000c);
273 mtdcr(DCRN_PEGPL_REGBAL(PCIE0), 0x10000000);
274 mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0x00007001);
275 mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0x68782800);
279 mtdcr(DCRN_PEGPL_REGBAH(PCIE1), 0x0000000c);
280 mtdcr(DCRN_PEGPL_REGBAL(PCIE1), 0x10001000);
281 mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0x00007001);
282 mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0x68782800);
286 mtdcr(DCRN_PEGPL_REGBAH(PCIE2), 0x0000000c);
287 mtdcr(DCRN_PEGPL_REGBA
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H A Dibm440gx_common.c116 mtdcr(DCRN_L2C0_ADDR, addr);
117 mtdcr(DCRN_L2C0_CMD, L2C_CMD_DIAG);
138 mtdcr(DCRN_L2C0_ADDR, 0);
139 mtdcr(DCRN_L2C0_CMD, L2C_CMD_CCP | L2C_CMD_CTE);
161 mtdcr(DCRN_SRAM0_DPC, mfdcr(DCRN_SRAM0_DPC) & ~SRAM_DPC_ENABLE);
162 mtdcr(DCRN_SRAM0_SB0CR, mfdcr(DCRN_SRAM0_SB0CR) & ~SRAM_SBCR_BU_MASK);
163 mtdcr(DCRN_SRAM0_SB1CR, mfdcr(DCRN_SRAM0_SB1CR) & ~SRAM_SBCR_BU_MASK);
164 mtdcr(DCRN_SRAM0_SB2CR, mfdcr(DCRN_SRAM0_SB2CR) & ~SRAM_SBCR_BU_MASK);
165 mtdcr(DCRN_SRAM0_SB3CR, mfdcr(DCRN_SRAM0_SB3CR) & ~SRAM_SBCR_BU_MASK);
170 mtdcr(DCRN_L2C0_CF
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H A Dppc403_pic.c80 mtdcr(DCRN_EXIER, ppc_cached_irq_mask[word]);
92 mtdcr(DCRN_EXIER, ppc_cached_irq_mask[word]);
104 mtdcr(DCRN_EXIER, ppc_cached_irq_mask[word]);
105 mtdcr(DCRN_EXISR, (1 << (31 - bit)));
119 mtdcr(DCRN_EXIER, ppc_cached_irq_mask[0]);
H A Dppc4xx_dma.c50 mtdcr(DCRN_DMASAH0 + dmanr*2, (u32)(src_addr >> 32));
52 mtdcr(DCRN_DMASA0 + dmanr*2, (u32)src_addr);
65 mtdcr(DCRN_DMADAH0 + dmanr*2, (u32)(dst_addr >> 32));
67 mtdcr(DCRN_DMADA0 + dmanr*2, (u32)dst_addr);
110 mtdcr(DCRN_DMACR0 + (dmanr * 0x8), control);
119 mtdcr(DCRN_DMASR, status_bits[dmanr]);
137 mtdcr(DCRN_DMACR0 + (dmanr * 0x8), control);
160 mtdcr(DCRN_DMACR0 + (dmanr * 0x8), control);
240 mtdcr(DCRN_DMACT0 + (dmanr * 0x8), count);
391 mtdcr(DCRN_DMACR
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H A Dibm44x_common.c111 mtdcr(DCRN_SDRAM0_CFGADDR, SDRAM0_B0CR);
114 mtdcr(DCRN_SDRAM0_CFGADDR, SDRAM0_B1CR);
117 mtdcr(DCRN_SDRAM0_CFGADDR, SDRAM0_B2CR);
120 mtdcr(DCRN_SDRAM0_CFGADDR, SDRAM0_B3CR);
H A Dppc4xx_sgdma.c41 mtdcr(DCRN_ASGH0 + (dmanr * 0x8), (u32)(sg_addr >> 32));
43 mtdcr(DCRN_ASG0 + (dmanr * 0x8), (u32)sg_addr);
171 mtdcr(DCRN_ASGC, sg_command); /* start transfer */
194 mtdcr(DCRN_ASGC, sg_command); /* stop transfer */
416 mtdcr(DCRN_ASGC, sg_command);
H A Dxilinx_pic.c36 #define intc_out_be32(addr, mask) mtdcr((addr), (mask))
H A Dppc4xx_setup.c170 mtdcr(DCRN_CHCR1, mfdcr(DCRN_CHCR1) & ~CHR1_CETE);
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/include/asm-powerpc/
H A Ddcr-native.h32 #define dcr_write(host, dcr_n, value) mtdcr(dcr_n, value)
46 #define mtdcr(rn, v) \ macro
49 asm volatile("mtdcr " __stringify(rn) ",%0" \
58 mtdcr(base ## _CFGADDR, base ## _ ## reg); \
64 mtdcr(base ## _CFGADDR, base ## _ ## reg); \
65 mtdcr(base ## _CFGDATA, data); \
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/arch/powerpc/sysdev/
H A Ddcr-low.S32 mtdcr 0,r4; blr
37 mtdcr dcr,r4; blr
H A Duic.c73 mtdcr(uic->dcrbase + UIC_ER, er);
87 mtdcr(uic->dcrbase + UIC_ER, er);
98 mtdcr(uic->dcrbase + UIC_SR, 1 << (31-src));
140 mtdcr(uic->dcrbase + UIC_PR, pr);
141 mtdcr(uic->dcrbase + UIC_TR, tr);
257 mtdcr(uic->dcrbase + UIC_ER, 0);
258 mtdcr(uic->dcrbase + UIC_CR, 0);
259 mtdcr(uic->dcrbase + UIC_TR, 0);
261 mtdcr(uic->dcrbase + UIC_SR, 0xffffffff);
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/arch/powerpc/boot/
H A D44x.c32 mtdcr(DCRN_SDRAM0_CFGADDR, sdram_bxcr[i]);
H A Ddcr.h10 #define mtdcr(rn, val) \ macro
11 asm volatile("mtdcr %0,%1" : : "i"(rn), "r"(val))
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/arch/ppc/boot/simple/rw4/
H A Drw4_init_brd.S218 mtdcr ebiu0_brcr0,r10
221 mtdcr ebiu0_brcrh0,r10
228 mtdcr ebiu0_brcr1,r10
231 mtdcr ebiu0_brcrh1,r10
238 mtdcr ebiu0_brcr2,r10
241 mtdcr ebiu0_brcrh2,r10
248 mtdcr ebiu0_brcr3,r10
251 mtdcr ebiu0_brcrh3,r10
258 mtdcr ebiu0_brcr4,r10
261 mtdcr ebiu0_brcrh
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H A Drw4_init.S57 mtdcr pb0pesr,r10 # to load RAM image via RiscWatch
59 mtdcr pb0pear,r10
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/include/asm-ppc/
H A Docp.h152 mtdcr(DCRN_CPMFR, mfdcr(DCRN_CPMFR) | odev->def->pm);
158 mtdcr(DCRN_CPMFR, mfdcr(DCRN_CPMFR) & ~odev->def->pm);
H A Dibm44x.h135 mtdcr(DCRN_CPR_CONFIG_ADDR, offset); \
138 mtdcr(DCRN_CPR_CONFIG_ADDR, offset); \
139 mtdcr(DCRN_CPR_CONFIG_DATA, data);})
185 mtdcr(DCRN_SDR_CONFIG_ADDR, offset); \
188 mtdcr(DCRN_SDR_CONFIG_ADDR, offset); \
189 mtdcr(DCRN_SDR_CONFIG_DATA,data);})
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/arch/ppc/platforms/4xx/
H A Dep405.c156 mtdcr(DCRN_UIC_PR(DCRN_UIC0_BASE), 0xffffff80); /* set the polarity */
157 mtdcr(DCRN_UIC_SR(DCRN_UIC0_BASE), 0x00000060); /* clear bogus interrupts */
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/arch/ppc/boot/simple/
H A Dmisc.c108 mtdcr(DCRN_MALCR(DCRN_MAL_BASE), MALCR_MMSR);
H A Dembed_config.c785 mtdcr(DCRN_MALCR(DCRN_MAL_BASE), MALCR_MMSR); /* 1st reset MAL */
844 mtdcr(DCRN_CHCR0, (chcr0 & 0xffffe000) | 0x103e);
853 mtdcr(DCRN_MALCR(DCRN_MAL_BASE), MALCR_MMSR); /* 1st reset MAL */
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/drivers/net/ibm_emac/
H A Dibm_emac_core.c100 mtdcr(0xf3, mfdcr(0xf3) | (1 << idx));
114 mtdcr(0xf3, mfdcr(0xf3) & ~(1 << idx));
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/arch/ppc/4xx_io/
H A Dserial_sicc.c308 mtdcr(DCRN_CICCR, value);

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