Lines Matching refs:mtdcr
50 mtdcr(DCRN_DMASAH0 + dmanr*2, (u32)(src_addr >> 32));
52 mtdcr(DCRN_DMASA0 + dmanr*2, (u32)src_addr);
65 mtdcr(DCRN_DMADAH0 + dmanr*2, (u32)(dst_addr >> 32));
67 mtdcr(DCRN_DMADA0 + dmanr*2, (u32)dst_addr);
110 mtdcr(DCRN_DMACR0 + (dmanr * 0x8), control);
119 mtdcr(DCRN_DMASR, status_bits[dmanr]);
137 mtdcr(DCRN_DMACR0 + (dmanr * 0x8), control);
160 mtdcr(DCRN_DMACR0 + (dmanr * 0x8), control);
240 mtdcr(DCRN_DMACT0 + (dmanr * 0x8), count);
391 mtdcr(DCRN_DMACR0 + (dmanr * 0x8), control);
419 mtdcr(DCRN_DMACR0 + (dmanr * 0x8), control);
469 mtdcr(DCRN_POL, polarity);
471 mtdcr(DCRN_DMACR0 + (dmanr * 0x8), control);
495 mtdcr(DCRN_DMASR, 0xffffffff); /* clear status register */
574 mtdcr(DCRN_DMACR0 + (dmanr * 0x8), control);
617 mtdcr(DCRN_DMASR, ((u32)DMA_CH0_ERR | (u32)DMA_CS0 | (u32)DMA_TS0) >> dmanr);
638 mtdcr(DCRN_DMACT0 + (dmanr * 0x8), ctc);
657 mtdcr(DCRN_DMACT0 + (dmanr * 0x8), ctc);
683 mtdcr(DCRN_DMACT0 + (dmanr * 0x8), ctc);