1#define VESTA 2#include "ppc_40x.h" 3# 4 .align 2 5 .text 6# 7# added by linguohui 8 .extern initb_ebiu0, initb_config, hdw_init_finish 9 .extern initb_hsmc0, initb_hsmc1, initb_cache 10# end added 11 .globl HdwInit 12# 13HdwInit: 14# 15#-----------------------------------------------------------------------* 16# If we are not executing from the FLASH get out * 17#-----------------------------------------------------------------------* 18# SAW keep this or comment out a la Hawthorne? 19# r3 contains NIP when used with Linux 20# rlwinm r28, r3, 8, 24, 31 # if MSB == 0xFF -> FLASH address 21# cmpwi r28, 0xff 22# bne locn01 23# 24# 25#------------------------------------------------------------------------ 26# Init_cpu. Bank registers are setup for the IBM STB. 27#------------------------------------------------------------------------ 28# 29# Setup processor core clock to be driven off chip. This is GPI4 bit 30# twenty. Setup Open Drain, Output Select, Three-State Control, and 31# Three-State Select registers. 32# 33 34 35 pb0pesr = 0x054 36 pb0pear = 0x056 37 38 mflr r30 39 40#----------------------------------------------------------------------------- 41# Vectors will be at 0x1F000000 42# Dummy Machine check handler just does RFI before true handler gets installed 43#----------------------------------------------------------------------------- 44#ifdef SDRAM16MB 45 lis r10,0x0000 46 addi r10,r10,0x0000 47#else 48 lis r10,0x1F00 49 addi r10,r10,0x0000 50#endif 51 52 mtspr evpr,r10 #EVPR: 0x0 or 0x1f000000 depending 53 isync # on SDRAM memory model used. 54 55 lis r10,0xFFFF # clear PB0_PESR because some 56 ori r10,r10,0xFFFF # transitions from flash,changed by linguohui 57 mtdcr pb0pesr,r10 # to load RAM image via RiscWatch 58 lis r10,0x0000 # cause PB0_PESR machine checks 59 mtdcr pb0pear,r10 60 addis r10,r10,0x0000 # clear the 61 mtxer r10 # XER just in case... 62 63 bl initb_ebiu0 # init EBIU 64 65 bl initb_config # config PPC and board 66 67 68 69 70#------------------------------------------------------------------------ 71# EVPR setup moved to top of this function. 72#------------------------------------------------------------------------ 73# 74 mtlr r30 75 blr 76 .end 77