Lines Matching refs:mtdcr
116 mtdcr(DCRN_L2C0_ADDR, addr);
117 mtdcr(DCRN_L2C0_CMD, L2C_CMD_DIAG);
138 mtdcr(DCRN_L2C0_ADDR, 0);
139 mtdcr(DCRN_L2C0_CMD, L2C_CMD_CCP | L2C_CMD_CTE);
161 mtdcr(DCRN_SRAM0_DPC, mfdcr(DCRN_SRAM0_DPC) & ~SRAM_DPC_ENABLE);
162 mtdcr(DCRN_SRAM0_SB0CR, mfdcr(DCRN_SRAM0_SB0CR) & ~SRAM_SBCR_BU_MASK);
163 mtdcr(DCRN_SRAM0_SB1CR, mfdcr(DCRN_SRAM0_SB1CR) & ~SRAM_SBCR_BU_MASK);
164 mtdcr(DCRN_SRAM0_SB2CR, mfdcr(DCRN_SRAM0_SB2CR) & ~SRAM_SBCR_BU_MASK);
165 mtdcr(DCRN_SRAM0_SB3CR, mfdcr(DCRN_SRAM0_SB3CR) & ~SRAM_SBCR_BU_MASK);
170 mtdcr(DCRN_L2C0_CFG, r);
172 mtdcr(DCRN_L2C0_ADDR, 0);
175 mtdcr(DCRN_L2C0_CMD, L2C_CMD_HCC);
179 mtdcr(DCRN_L2C0_CMD, L2C_CMD_CCP | L2C_CMD_CTE);
184 mtdcr(DCRN_L2C0_SNP0, r);
188 mtdcr(DCRN_L2C0_SNP1, r);
198 mtdcr(DCRN_L2C0_CFG, r);
214 mtdcr(DCRN_L2C0_CFG, r);
217 mtdcr(DCRN_SRAM0_DPC, mfdcr(DCRN_SRAM0_DPC) | SRAM_DPC_ENABLE);
218 mtdcr(DCRN_SRAM0_SB0CR,
220 mtdcr(DCRN_SRAM0_SB1CR,
222 mtdcr(DCRN_SRAM0_SB2CR,
224 mtdcr(DCRN_SRAM0_SB3CR,