1/* 2 * include/asm-ppc/ibm44x.h 3 * 4 * PPC44x definitions 5 * 6 * Matt Porter <mporter@kernel.crashing.org> 7 * 8 * Copyright 2002-2005 MontaVista Software Inc. 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms of the GNU General Public License as published by the 12 * Free Software Foundation; either version 2 of the License, or (at your 13 * option) any later version. 14 */ 15 16#ifdef __KERNEL__ 17#ifndef __ASM_IBM44x_H__ 18#define __ASM_IBM44x_H__ 19 20 21#ifndef NR_BOARD_IRQS 22#define NR_BOARD_IRQS 0 23#endif 24 25#define _IO_BASE isa_io_base 26#define _ISA_MEM_BASE isa_mem_base 27#define PCI_DRAM_OFFSET pci_dram_offset 28 29/* TLB entry offset/size used for pinning kernel lowmem */ 30#define PPC44x_PIN_SHIFT 28 31#define PPC_PIN_SIZE (1 << PPC44x_PIN_SHIFT) 32 33/* Lowest TLB slot consumed by the default pinned TLBs */ 34#define PPC44x_LOW_SLOT 63 35 36/* 37 * Least significant 32-bits and extended real page number (ERPN) of 38 * UART0 physical address location for early serial text debug 39 */ 40#if defined(CONFIG_440SP) 41#define UART0_PHYS_ERPN 1 42#define UART0_PHYS_IO_BASE 0xf0000200 43#elif defined(CONFIG_440SPE) 44#define UART0_PHYS_ERPN 4 45#define UART0_PHYS_IO_BASE 0xf0000200 46#elif defined(CONFIG_440EP) 47#define UART0_PHYS_IO_BASE 0xe0000000 48#else 49#define UART0_PHYS_ERPN 1 50#define UART0_PHYS_IO_BASE 0x40000200 51#endif 52 53 54/* 55 * Standard 4GB "page" definitions 56 */ 57#if defined(CONFIG_440SP) 58#define PPC44x_IO_PAGE 0x0000000100000000ULL 59#define PPC44x_PCICFG_PAGE 0x0000000900000000ULL 60#define PPC44x_PCIIO_PAGE PPC44x_PCICFG_PAGE 61#define PPC44x_PCIMEM_PAGE 0x0000000a00000000ULL 62#elif defined(CONFIG_440SPE) 63#define PPC44x_IO_PAGE 0x0000000400000000ULL 64#define PPC44x_PCICFG_PAGE 0x0000000c00000000ULL 65#define PPC44x_PCIIO_PAGE PPC44x_PCICFG_PAGE 66#define PPC44x_PCIMEM_PAGE 0x0000000d00000000ULL 67#elif defined(CONFIG_440EP) 68#define PPC44x_IO_PAGE 0x0000000000000000ULL 69#define PPC44x_PCICFG_PAGE 0x0000000000000000ULL 70#define PPC44x_PCIIO_PAGE PPC44x_PCICFG_PAGE 71#define PPC44x_PCIMEM_PAGE 0x0000000000000000ULL 72#else 73#define PPC44x_IO_PAGE 0x0000000100000000ULL 74#define PPC44x_PCICFG_PAGE 0x0000000200000000ULL 75#define PPC44x_PCIIO_PAGE PPC44x_PCICFG_PAGE 76#define PPC44x_PCIMEM_PAGE 0x0000000300000000ULL 77#endif 78 79/* 80 * 36-bit trap ranges 81 */ 82#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) 83#define PPC44x_IO_LO 0xf0000000UL 84#define PPC44x_IO_HI 0xf0000fffUL 85#define PPC44x_PCI0CFG_LO 0x0ec00000UL 86#define PPC44x_PCI0CFG_HI 0x0ec00007UL 87#define PPC44x_PCI1CFG_LO 0x1ec00000UL 88#define PPC44x_PCI1CFG_HI 0x1ec00007UL 89#define PPC44x_PCI2CFG_LO 0x2ec00000UL 90#define PPC44x_PCI2CFG_HI 0x2ec00007UL 91#define PPC44x_PCIMEM_LO 0x80000000UL 92#define PPC44x_PCIMEM_HI 0xdfffffffUL 93#elif defined(CONFIG_440EP) 94#define PPC44x_IO_LO 0xef500000UL 95#define PPC44x_IO_HI 0xefffffffUL 96#define PPC44x_PCI0CFG_LO 0xeec00000UL 97#define PPC44x_PCI0CFG_HI 0xeecfffffUL 98#define PPC44x_PCIMEM_LO 0xa0000000UL 99#define PPC44x_PCIMEM_HI 0xdfffffffUL 100#else 101#define PPC44x_IO_LO 0x40000000UL 102#define PPC44x_IO_HI 0x40000fffUL 103#define PPC44x_PCI0CFG_LO 0x0ec00000UL 104#define PPC44x_PCI0CFG_HI 0x0ec00007UL 105#define PPC44x_PCIMEM_LO 0x80002000UL 106#define PPC44x_PCIMEM_HI 0xffffffffUL 107#endif 108 109/* 110 * The "residual" board information structure the boot loader passes 111 * into the kernel. 112 */ 113#ifndef __ASSEMBLY__ 114 115/* 116 * DCRN definitions 117 */ 118 119 120/* CPRs (440GX and 440SP/440SPe) */ 121#define DCRN_CPR_CONFIG_ADDR 0xc 122#define DCRN_CPR_CONFIG_DATA 0xd 123 124#define DCRN_CPR_CLKUPD 0x0020 125#define DCRN_CPR_PLLC 0x0040 126#define DCRN_CPR_PLLD 0x0060 127#define DCRN_CPR_PRIMAD 0x0080 128#define DCRN_CPR_PRIMBD 0x00a0 129#define DCRN_CPR_OPBD 0x00c0 130#define DCRN_CPR_PERD 0x00e0 131#define DCRN_CPR_MALD 0x0100 132 133/* CPRs read/write helper macros */ 134#define CPR_READ(offset) ({\ 135 mtdcr(DCRN_CPR_CONFIG_ADDR, offset); \ 136 mfdcr(DCRN_CPR_CONFIG_DATA);}) 137#define CPR_WRITE(offset, data) ({\ 138 mtdcr(DCRN_CPR_CONFIG_ADDR, offset); \ 139 mtdcr(DCRN_CPR_CONFIG_DATA, data);}) 140 141/* SDRs (440GX and 440SP/440SPe) */ 142#define DCRN_SDR_CONFIG_ADDR 0xe 143#define DCRN_SDR_CONFIG_DATA 0xf 144#define DCRN_SDR_PFC0 0x4100 145#define DCRN_SDR_PFC1 0x4101 146#define DCRN_SDR_PFC1_EPS 0x1c00000 147#define DCRN_SDR_PFC1_EPS_SHIFT 22 148#define DCRN_SDR_PFC1_RMII 0x02000000 149#define DCRN_SDR_MFR 0x4300 150#define DCRN_SDR_MFR_TAH0 0x80000000 /* TAHOE0 Enable */ 151#define DCRN_SDR_MFR_TAH1 0x40000000 /* TAHOE1 Enable */ 152#define DCRN_SDR_MFR_PCM 0x10000000 /* PPC440GP irq compat mode */ 153#define DCRN_SDR_MFR_ECS 0x08000000 /* EMAC int clk */ 154#define DCRN_SDR_MFR_T0TXFL 0x00080000 155#define DCRN_SDR_MFR_T0TXFH 0x00040000 156#define DCRN_SDR_MFR_T1TXFL 0x00020000 157#define DCRN_SDR_MFR_T1TXFH 0x00010000 158#define DCRN_SDR_MFR_E0TXFL 0x00008000 159#define DCRN_SDR_MFR_E0TXFH 0x00004000 160#define DCRN_SDR_MFR_E0RXFL 0x00002000 161#define DCRN_SDR_MFR_E0RXFH 0x00001000 162#define DCRN_SDR_MFR_E1TXFL 0x00000800 163#define DCRN_SDR_MFR_E1TXFH 0x00000400 164#define DCRN_SDR_MFR_E1RXFL 0x00000200 165#define DCRN_SDR_MFR_E1RXFH 0x00000100 166#define DCRN_SDR_MFR_E2TXFL 0x00000080 167#define DCRN_SDR_MFR_E2TXFH 0x00000040 168#define DCRN_SDR_MFR_E2RXFL 0x00000020 169#define DCRN_SDR_MFR_E2RXFH 0x00000010 170#define DCRN_SDR_MFR_E3TXFL 0x00000008 171#define DCRN_SDR_MFR_E3TXFH 0x00000004 172#define DCRN_SDR_MFR_E3RXFL 0x00000002 173#define DCRN_SDR_MFR_E3RXFH 0x00000001 174#define DCRN_SDR_UART0 0x0120 175#define DCRN_SDR_UART1 0x0121 176 177#ifdef CONFIG_440EP 178#define DCRN_SDR_UART2 0x0122 179#define DCRN_SDR_UART3 0x0123 180#define DCRN_SDR_CUST0 0x4000 181#endif 182 183/* SDR read/write helper macros */ 184#define SDR_READ(offset) ({\ 185 mtdcr(DCRN_SDR_CONFIG_ADDR, offset); \ 186 mfdcr(DCRN_SDR_CONFIG_DATA);}) 187#define SDR_WRITE(offset, data) ({\ 188 mtdcr(DCRN_SDR_CONFIG_ADDR, offset); \ 189 mtdcr(DCRN_SDR_CONFIG_DATA,data);}) 190 191/* DMA (excluding 440SP/440SPe) */ 192#define DCRN_DMA0_BASE 0x100 193#define DCRN_DMA1_BASE 0x108 194#define DCRN_DMA2_BASE 0x110 195#define DCRN_DMA3_BASE 0x118 196#define DCRN_DMASR_BASE 0x120 197#define DCRNCAP_DMA_SG 1 /* have DMA scatter/gather capability */ 198#define DCRN_MAL_BASE 0x180 199 200#ifdef CONFIG_440EP 201#define DCRN_DMA2P40_BASE 0x300 202#define DCRN_DMA2P41_BASE 0x308 203#define DCRN_DMA2P42_BASE 0x310 204#define DCRN_DMA2P43_BASE 0x318 205#define DCRN_DMA2P4SR_BASE 0x320 206#endif 207 208/* UIC */ 209#define DCRN_UIC0_BASE 0xc0 210#define DCRN_UIC1_BASE 0xd0 211#define UIC0 DCRN_UIC0_BASE 212#define UIC1 DCRN_UIC1_BASE 213 214#ifdef CONFIG_440SPE 215#define DCRN_UIC2_BASE 0xe0 216#define DCRN_UIC3_BASE 0xf0 217#define UIC2 DCRN_UIC2_BASE 218#define UIC3 DCRN_UIC3_BASE 219#else 220#define DCRN_UIC2_BASE 0x210 221#define DCRN_UICB_BASE 0x200 222#define UIC2 DCRN_UIC2_BASE 223#define UICB DCRN_UICB_BASE 224#endif 225 226#define DCRN_UIC_SR(base) (base + 0x0) 227#define DCRN_UIC_ER(base) (base + 0x2) 228#define DCRN_UIC_CR(base) (base + 0x3) 229#define DCRN_UIC_PR(base) (base + 0x4) 230#define DCRN_UIC_TR(base) (base + 0x5) 231#define DCRN_UIC_MSR(base) (base + 0x6) 232#define DCRN_UIC_VR(base) (base + 0x7) 233#define DCRN_UIC_VCR(base) (base + 0x8) 234 235#define UIC0_UIC1NC 0x00000002 236 237#ifdef CONFIG_440SPE 238#define UIC0_UIC1NC 0x00000002 239#define UIC0_UIC2NC 0x00200000 240#define UIC0_UIC3NC 0x00008000 241#endif 242 243#define UICB_UIC0NC 0x40000000 244#define UICB_UIC1NC 0x10000000 245#define UICB_UIC2NC 0x04000000 246 247/* 440 MAL DCRs */ 248#define DCRN_MALCR(base) (base + 0x0) /* Configuration */ 249#define DCRN_MALESR(base) (base + 0x1) /* Error Status */ 250#define DCRN_MALIER(base) (base + 0x2) /* Interrupt Enable */ 251#define DCRN_MALTXCASR(base) (base + 0x4) /* Tx Channel Active Set */ 252#define DCRN_MALTXCARR(base) (base + 0x5) /* Tx Channel Active Reset */ 253#define DCRN_MALTXEOBISR(base) (base + 0x6) /* Tx End of Buffer Interrupt Status */ 254#define DCRN_MALTXDEIR(base) (base + 0x7) /* Tx Descriptor Error Interrupt */ 255#define DCRN_MALRXCASR(base) (base + 0x10) /* Rx Channel Active Set */ 256#define DCRN_MALRXCARR(base) (base + 0x11) /* Rx Channel Active Reset */ 257#define DCRN_MALRXEOBISR(base) (base + 0x12) /* Rx End of Buffer Interrupt Status */ 258#define DCRN_MALRXDEIR(base) (base + 0x13) /* Rx Descriptor Error Interrupt */ 259#define DCRN_MALTXCTP0R(base) (base + 0x20) /* Channel Tx 0 Channel Table Pointer */ 260#define DCRN_MALTXCTP1R(base) (base + 0x21) /* Channel Tx 1 Channel Table Pointer */ 261#define DCRN_MALTXCTP2R(base) (base + 0x22) /* Channel Tx 2 Channel Table Pointer */ 262#define DCRN_MALTXCTP3R(base) (base + 0x23) /* Channel Tx 3 Channel Table Pointer */ 263#define DCRN_MALRXCTP0R(base) (base + 0x40) /* Channel Rx 0 Channel Table Pointer */ 264#define DCRN_MALRXCTP1R(base) (base + 0x41) /* Channel Rx 1 Channel Table Pointer */ 265#define DCRN_MALRCBS0(base) (base + 0x60) /* Channel Rx 0 Channel Buffer Size */ 266#define DCRN_MALRCBS1(base) (base + 0x61) /* Channel Rx 1 Channel Buffer Size */ 267 268/* Compatibility DCRN's */ 269#define DCRN_MALRXCTP2R(base) ((base) + 0x42) /* Channel Rx 2 Channel Table Pointer */ 270#define DCRN_MALRXCTP3R(base) ((base) + 0x43) /* Channel Rx 3 Channel Table Pointer */ 271#define DCRN_MALTXCTP4R(base) ((base) + 0x24) /* Channel Tx 4 Channel Table Pointer */ 272#define DCRN_MALTXCTP5R(base) ((base) + 0x25) /* Channel Tx 5 Channel Table Pointer */ 273#define DCRN_MALTXCTP6R(base) ((base) + 0x26) /* Channel Tx 6 Channel Table Pointer */ 274#define DCRN_MALTXCTP7R(base) ((base) + 0x27) /* Channel Tx 7 Channel Table Pointer */ 275#define DCRN_MALRCBS2(base) ((base) + 0x62) /* Channel Rx 2 Channel Buffer Size */ 276#define DCRN_MALRCBS3(base) ((base) + 0x63) /* Channel Rx 3 Channel Buffer Size */ 277 278#define MALCR_MMSR 0x80000000 /* MAL Software reset */ 279#define MALCR_PLBP_1 0x00400000 /* MAL reqest priority: */ 280#define MALCR_PLBP_2 0x00800000 /* lowsest is 00 */ 281#define MALCR_PLBP_3 0x00C00000 /* highest */ 282#define MALCR_GA 0x00200000 /* Guarded Active Bit */ 283#define MALCR_OA 0x00100000 /* Ordered Active Bit */ 284#define MALCR_PLBLE 0x00080000 /* PLB Lock Error Bit */ 285#define MALCR_PLBLT_1 0x00040000 /* PLB Latency Timer */ 286#define MALCR_PLBLT_2 0x00020000 287#define MALCR_PLBLT_3 0x00010000 288#define MALCR_PLBLT_4 0x00008000 289#ifdef CONFIG_440GP 290#define MALCR_PLBLT_DEFAULT 0x00330000 /* PLB Latency Timer default */ 291#else 292#define MALCR_PLBLT_DEFAULT 0x00ff0000 /* PLB Latency Timer default */ 293#endif 294#define MALCR_PLBB 0x00004000 /* PLB Burst Deactivation Bit */ 295#define MALCR_OPBBL 0x00000080 /* OPB Lock Bit */ 296#define MALCR_EOPIE 0x00000004 /* End Of Packet Interrupt Enable */ 297#define MALCR_LEA 0x00000002 /* Locked Error Active */ 298#define MALCR_MSD 0x00000001 /* MAL Scroll Descriptor Bit */ 299/* DCRN_MALESR */ 300#define MALESR_EVB 0x80000000 /* Error Valid Bit */ 301#define MALESR_CIDRX 0x40000000 /* Channel ID Receive */ 302#define MALESR_DE 0x00100000 /* Descriptor Error */ 303#define MALESR_OEN 0x00080000 /* OPB Non-Fullword Error */ 304#define MALESR_OTE 0x00040000 /* OPB Timeout Error */ 305#define MALESR_OSE 0x00020000 /* OPB Slave Error */ 306#define MALESR_PEIN 0x00010000 /* PLB Bus Error Indication */ 307#define MALESR_DEI 0x00000010 /* Descriptor Error Interrupt */ 308#define MALESR_ONEI 0x00000008 /* OPB Non-Fullword Error Interrupt */ 309#define MALESR_OTEI 0x00000004 /* OPB Timeout Error Interrupt */ 310#define MALESR_OSEI 0x00000002 /* OPB Slace Error Interrupt */ 311#define MALESR_PBEI 0x00000001 /* PLB Bus Error Interrupt */ 312/* DCRN_MALIER */ 313#define MALIER_DE 0x00000010 /* Descriptor Error Interrupt Enable */ 314#define MALIER_NE 0x00000008 /* OPB Non-word Transfer Int Enable */ 315#define MALIER_TE 0x00000004 /* OPB Time Out Error Interrupt Enable */ 316#define MALIER_OPBE 0x00000002 /* OPB Slave Error Interrupt Enable */ 317#define MALIER_PLBE 0x00000001 /* PLB Error Interrupt Enable */ 318/* DCRN_MALTXEOBISR */ 319#define MALOBISR_CH0 0x80000000 /* EOB channel 1 bit */ 320#define MALOBISR_CH2 0x40000000 /* EOB channel 2 bit */ 321 322#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) 323/* 440SP/440SPe PLB Arbiter DCRs */ 324#define DCRN_PLB_REVID 0x080 /* PLB Revision ID */ 325#define DCRN_PLB_CCR 0x088 /* PLB Crossbar Control */ 326 327#define DCRN_PLB0_ACR 0x081 /* PLB Arbiter Control */ 328#define DCRN_PLB0_BESRL 0x082 /* PLB Error Status */ 329#define DCRN_PLB0_BESRH 0x083 /* PLB Error Status */ 330#define DCRN_PLB0_BEARL 0x084 /* PLB Error Address Low */ 331#define DCRN_PLB0_BEARH 0x085 /* PLB Error Address High */ 332 333#define DCRN_PLB1_ACR 0x089 /* PLB Arbiter Control */ 334#define DCRN_PLB1_BESRL 0x08a /* PLB Error Status */ 335#define DCRN_PLB1_BESRH 0x08b /* PLB Error Status */ 336#define DCRN_PLB1_BEARL 0x08c /* PLB Error Address Low */ 337#define DCRN_PLB1_BEARH 0x08d /* PLB Error Address High */ 338#else 339/* 440GP/GX PLB Arbiter DCRs */ 340#define DCRN_PLB0_REVID 0x082 /* PLB Arbiter Revision ID */ 341#define DCRN_PLB0_ACR 0x083 /* PLB Arbiter Control */ 342#define DCRN_PLB0_BESR 0x084 /* PLB Error Status */ 343#define DCRN_PLB0_BEARL 0x086 /* PLB Error Address Low */ 344#define DCRN_PLB0_BEAR DCRN_PLB0_BEARL /* 40x compatibility */ 345#define DCRN_PLB0_BEARH 0x087 /* PLB Error Address High */ 346#endif 347 348/* 440GP/GX PLB to OPB bridge DCRs */ 349#define DCRN_POB0_BESR0 0x090 350#define DCRN_POB0_BESR1 0x094 351#define DCRN_POB0_BEARL 0x092 352#define DCRN_POB0_BEARH 0x093 353 354/* 440GP/GX OPB to PLB bridge DCRs */ 355#define DCRN_OPB0_BSTAT 0x0a9 356#define DCRN_OPB0_BEARL 0x0aa 357#define DCRN_OPB0_BEARH 0x0ab 358 359/* 440GP Clock, PM, chip control */ 360#define DCRN_CPC0_SR 0x0b0 361#define DCRN_CPC0_ER 0x0b1 362#define DCRN_CPC0_FR 0x0b2 363#define DCRN_CPC0_SYS0 0x0e0 364#define DCRN_CPC0_SYS1 0x0e1 365#define DCRN_CPC0_CUST0 0x0e2 366#define DCRN_CPC0_CUST1 0x0e3 367#define DCRN_CPC0_STRP0 0x0e4 368#define DCRN_CPC0_STRP1 0x0e5 369#define DCRN_CPC0_STRP2 0x0e6 370#define DCRN_CPC0_STRP3 0x0e7 371#define DCRN_CPC0_GPIO 0x0e8 372#define DCRN_CPC0_PLB 0x0e9 373#define DCRN_CPC0_CR1 0x0ea 374#define DCRN_CPC0_CR0 0x0eb 375#define DCRN_CPC0_MIRQ0 0x0ec 376#define DCRN_CPC0_MIRQ1 0x0ed 377#define DCRN_CPC0_JTAGID 0x0ef 378 379/* 440GP DMA controller DCRs */ 380#define DCRN_DMACR0 (DCRN_DMA0_BASE + 0x0) /* DMA Channel Control 0 */ 381#define DCRN_DMACT0 (DCRN_DMA0_BASE + 0x1) /* DMA Count 0 */ 382#define DCRN_DMASAH0 (DCRN_DMA0_BASE + 0x2) /* DMA Src Addr High 0 */ 383#define DCRN_DMASA0 (DCRN_DMA0_BASE + 0x3) /* DMA Src Addr Low 0 */ 384#define DCRN_DMADAH0 (DCRN_DMA0_BASE + 0x4) /* DMA Dest Addr High 0 */ 385#define DCRN_DMADA0 (DCRN_DMA0_BASE + 0x5) /* DMA Dest Addr Low 0 */ 386#define DCRN_ASGH0 (DCRN_DMA0_BASE + 0x6) /* DMA SG Desc Addr High 0 */ 387#define DCRN_ASG0 (DCRN_DMA0_BASE + 0x7) /* DMA SG Desc Addr Low 0 */ 388 389#define DCRN_DMACR1 (DCRN_DMA1_BASE + 0x0) /* DMA Channel Control 1 */ 390#define DCRN_DMACT1 (DCRN_DMA1_BASE + 0x1) /* DMA Count 1 */ 391#define DCRN_DMASAH1 (DCRN_DMA1_BASE + 0x2) /* DMA Src Addr High 1 */ 392#define DCRN_DMASA1 (DCRN_DMA1_BASE + 0x3) /* DMA Src Addr Low 1 */ 393#define DCRN_DMADAH1 (DCRN_DMA1_BASE + 0x4) /* DMA Dest Addr High 1 */ 394#define DCRN_DMADA1 (DCRN_DMA1_BASE + 0x5) /* DMA Dest Addr Low 1 */ 395#define DCRN_ASGH1 (DCRN_DMA1_BASE + 0x6) /* DMA SG Desc Addr High 1 */ 396#define DCRN_ASG1 (DCRN_DMA1_BASE + 0x7) /* DMA SG Desc Addr Low 1 */ 397 398#define DCRN_DMACR2 (DCRN_DMA2_BASE + 0x0) /* DMA Channel Control 2 */ 399#define DCRN_DMACT2 (DCRN_DMA2_BASE + 0x1) /* DMA Count 2 */ 400#define DCRN_DMASAH2 (DCRN_DMA2_BASE + 0x2) /* DMA Src Addr High 2 */ 401#define DCRN_DMASA2 (DCRN_DMA2_BASE + 0x3) /* DMA Src Addr Low 2 */ 402#define DCRN_DMADAH2 (DCRN_DMA2_BASE + 0x4) /* DMA Dest Addr High 2 */ 403#define DCRN_DMADA2 (DCRN_DMA2_BASE + 0x5) /* DMA Dest Addr Low 2 */ 404#define DCRN_ASGH2 (DCRN_DMA2_BASE + 0x6) /* DMA SG Desc Addr High 2 */ 405#define DCRN_ASG2 (DCRN_DMA2_BASE + 0x7) /* DMA SG Desc Addr Low 2 */ 406 407#define DCRN_DMACR3 (DCRN_DMA3_BASE + 0x0) /* DMA Channel Control 3 */ 408#define DCRN_DMACT3 (DCRN_DMA3_BASE + 0x1) /* DMA Count 3 */ 409#define DCRN_DMASAH3 (DCRN_DMA3_BASE + 0x2) /* DMA Src Addr High 3 */ 410#define DCRN_DMASA3 (DCRN_DMA3_BASE + 0x3) /* DMA Src Addr Low 3 */ 411#define DCRN_DMADAH3 (DCRN_DMA3_BASE + 0x4) /* DMA Dest Addr High 3 */ 412#define DCRN_DMADA3 (DCRN_DMA3_BASE + 0x5) /* DMA Dest Addr Low 3 */ 413#define DCRN_ASGH3 (DCRN_DMA3_BASE + 0x6) /* DMA SG Desc Addr High 3 */ 414#define DCRN_ASG3 (DCRN_DMA3_BASE + 0x7) /* DMA SG Desc Addr Low 3 */ 415 416#define DCRN_DMASR (DCRN_DMASR_BASE + 0x0) /* DMA Status Register */ 417#define DCRN_ASGC (DCRN_DMASR_BASE + 0x3) /* DMA Scatter/Gather Command */ 418#define DCRN_SLP (DCRN_DMASR_BASE + 0x5) /* DMA Sleep Register */ 419#define DCRN_POL (DCRN_DMASR_BASE + 0x6) /* DMA Polarity Register */ 420 421/* 440GP/440GX SDRAM controller DCRs */ 422#define DCRN_SDRAM0_CFGADDR 0x010 423#define DCRN_SDRAM0_CFGDATA 0x011 424 425#define SDRAM0_B0CR 0x40 426#define SDRAM0_B1CR 0x44 427#define SDRAM0_B2CR 0x48 428#define SDRAM0_B3CR 0x4c 429 430#define SDRAM_CONFIG_BANK_ENABLE 0x00000001 431#define SDRAM_CONFIG_SIZE_MASK 0x000e0000 432#define SDRAM_CONFIG_BANK_SIZE(reg) ((reg & SDRAM_CONFIG_SIZE_MASK) >> 17) 433#define SDRAM_CONFIG_SIZE_8M 0x00000001 434#define SDRAM_CONFIG_SIZE_16M 0x00000002 435#define SDRAM_CONFIG_SIZE_32M 0x00000003 436#define SDRAM_CONFIG_SIZE_64M 0x00000004 437#define SDRAM_CONFIG_SIZE_128M 0x00000005 438#define SDRAM_CONFIG_SIZE_256M 0x00000006 439#define SDRAM_CONFIG_SIZE_512M 0x00000007 440#define PPC44x_MEM_SIZE_8M 0x00800000 441#define PPC44x_MEM_SIZE_16M 0x01000000 442#define PPC44x_MEM_SIZE_32M 0x02000000 443#define PPC44x_MEM_SIZE_64M 0x04000000 444#define PPC44x_MEM_SIZE_128M 0x08000000 445#define PPC44x_MEM_SIZE_256M 0x10000000 446#define PPC44x_MEM_SIZE_512M 0x20000000 447#define PPC44x_MEM_SIZE_1G 0x40000000 448#define PPC44x_MEM_SIZE_2G 0x80000000 449 450/* 440SP/440SPe memory controller DCRs */ 451#define DCRN_MQ0_BS0BAS 0x40 452#if defined(CONFIG_440SP) 453#define MQ0_NUM_BANKS 2 454#elif defined(CONFIG_440SPE) 455#define MQ0_NUM_BANKS 4 456#endif 457 458#define MQ0_CONFIG_SIZE_MASK 0x0000fff0 459#define MQ0_CONFIG_SIZE_8M 0x0000ffc0 460#define MQ0_CONFIG_SIZE_16M 0x0000ff80 461#define MQ0_CONFIG_SIZE_32M 0x0000ff00 462#define MQ0_CONFIG_SIZE_64M 0x0000fe00 463#define MQ0_CONFIG_SIZE_128M 0x0000fc00 464#define MQ0_CONFIG_SIZE_256M 0x0000f800 465#define MQ0_CONFIG_SIZE_512M 0x0000f000 466#define MQ0_CONFIG_SIZE_1G 0x0000e000 467#define MQ0_CONFIG_SIZE_2G 0x0000c000 468#define MQ0_CONFIG_SIZE_4G 0x00008000 469 470/* Internal SRAM Controller 440GX/440SP/440SPe */ 471#define DCRN_SRAM0_BASE 0x000 472 473#define DCRN_SRAM0_SB0CR (DCRN_SRAM0_BASE + 0x020) 474#define DCRN_SRAM0_SB1CR (DCRN_SRAM0_BASE + 0x021) 475#define DCRN_SRAM0_SB2CR (DCRN_SRAM0_BASE + 0x022) 476#define DCRN_SRAM0_SB3CR (DCRN_SRAM0_BASE + 0x023) 477#define SRAM_SBCR_BAS0 0x80000000 478#define SRAM_SBCR_BAS1 0x80010000 479#define SRAM_SBCR_BAS2 0x80020000 480#define SRAM_SBCR_BAS3 0x80030000 481#define SRAM_SBCR_BU_MASK 0x00000180 482#define SRAM_SBCR_BS_64KB 0x00000800 483#define SRAM_SBCR_BU_RO 0x00000080 484#define SRAM_SBCR_BU_RW 0x00000180 485#define DCRN_SRAM0_BEAR (DCRN_SRAM0_BASE + 0x024) 486#define DCRN_SRAM0_BESR0 (DCRN_SRAM0_BASE + 0x025) 487#define DCRN_SRAM0_BESR1 (DCRN_SRAM0_BASE + 0x026) 488#define DCRN_SRAM0_PMEG (DCRN_SRAM0_BASE + 0x027) 489#define DCRN_SRAM0_CID (DCRN_SRAM0_BASE + 0x028) 490#define DCRN_SRAM0_REVID (DCRN_SRAM0_BASE + 0x029) 491#define DCRN_SRAM0_DPC (DCRN_SRAM0_BASE + 0x02a) 492#define SRAM_DPC_ENABLE 0x80000000 493 494/* L2 Cache Controller 440GX/440SP/440SPe */ 495#define DCRN_L2C0_CFG 0x030 496#define L2C_CFG_L2M 0x80000000 497#define L2C_CFG_ICU 0x40000000 498#define L2C_CFG_DCU 0x20000000 499#define L2C_CFG_DCW_MASK 0x1e000000 500#define L2C_CFG_TPC 0x01000000 501#define L2C_CFG_CPC 0x00800000 502#define L2C_CFG_FRAN 0x00200000 503#define L2C_CFG_SS_MASK 0x00180000 504#define L2C_CFG_SS_256 0x00000000 505#define L2C_CFG_CPIM 0x00040000 506#define L2C_CFG_TPIM 0x00020000 507#define L2C_CFG_LIM 0x00010000 508#define L2C_CFG_PMUX_MASK 0x00007000 509#define L2C_CFG_PMUX_SNP 0x00000000 510#define L2C_CFG_PMUX_IF 0x00001000 511#define L2C_CFG_PMUX_DF 0x00002000 512#define L2C_CFG_PMUX_DS 0x00003000 513#define L2C_CFG_PMIM 0x00000800 514#define L2C_CFG_TPEI 0x00000400 515#define L2C_CFG_CPEI 0x00000200 516#define L2C_CFG_NAM 0x00000100 517#define L2C_CFG_SMCM 0x00000080 518#define L2C_CFG_NBRM 0x00000040 519#define DCRN_L2C0_CMD 0x031 520#define L2C_CMD_CLR 0x80000000 521#define L2C_CMD_DIAG 0x40000000 522#define L2C_CMD_INV 0x20000000 523#define L2C_CMD_CCP 0x10000000 524#define L2C_CMD_CTE 0x08000000 525#define L2C_CMD_STRC 0x04000000 526#define L2C_CMD_STPC 0x02000000 527#define L2C_CMD_RPMC 0x01000000 528#define L2C_CMD_HCC 0x00800000 529#define DCRN_L2C0_ADDR 0x032 530#define DCRN_L2C0_DATA 0x033 531#define DCRN_L2C0_SR 0x034 532#define L2C_SR_CC 0x80000000 533#define L2C_SR_CPE 0x40000000 534#define L2C_SR_TPE 0x20000000 535#define L2C_SR_LRU 0x10000000 536#define L2C_SR_PCS 0x08000000 537#define DCRN_L2C0_REVID 0x035 538#define DCRN_L2C0_SNP0 0x036 539#define DCRN_L2C0_SNP1 0x037 540#define L2C_SNP_BA_MASK 0xffff0000 541#define L2C_SNP_SSR_MASK 0x0000f000 542#define L2C_SNP_SSR_32G 0x0000f000 543#define L2C_SNP_ESR 0x00000800 544 545/* 546 * PCI-X definitions 547 */ 548#define PCIX0_CFGA 0x0ec00000UL 549#define PCIX1_CFGA 0x1ec00000UL 550#define PCIX2_CFGA 0x2ec00000UL 551#define PCIX0_CFGD 0x0ec00004UL 552#define PCIX1_CFGD 0x1ec00004UL 553#define PCIX2_CFGD 0x2ec00004UL 554 555#define PCIX0_IO_BASE 0x0000000908000000ULL 556#define PCIX1_IO_BASE 0x0000000908000000ULL 557#define PCIX2_IO_BASE 0x0000000908000000ULL 558#define PCIX_IO_SIZE 0x00010000 559 560#ifdef CONFIG_440SP 561#define PCIX0_REG_BASE 0x000000090ec80000ULL 562#else 563#define PCIX0_REG_BASE 0x000000020ec80000ULL 564#endif 565#define PCIX_REG_OFFSET 0x10000000 566#define PCIX_REG_SIZE 0x200 567 568#define PCIX0_VENDID 0x000 569#define PCIX0_DEVID 0x002 570#define PCIX0_COMMAND 0x004 571#define PCIX0_STATUS 0x006 572#define PCIX0_REVID 0x008 573#define PCIX0_CLS 0x009 574#define PCIX0_CACHELS 0x00c 575#define PCIX0_LATTIM 0x00d 576#define PCIX0_HDTYPE 0x00e 577#define PCIX0_BIST 0x00f 578#define PCIX0_BAR0L 0x010 579#define PCIX0_BAR0H 0x014 580#define PCIX0_BAR1 0x018 581#define PCIX0_BAR2L 0x01c 582#define PCIX0_BAR2H 0x020 583#define PCIX0_BAR3 0x024 584#define PCIX0_CISPTR 0x028 585#define PCIX0_SBSYSVID 0x02c 586#define PCIX0_SBSYSID 0x02e 587#define PCIX0_EROMBA 0x030 588#define PCIX0_CAP 0x034 589#define PCIX0_RES0 0x035 590#define PCIX0_RES1 0x036 591#define PCIX0_RES2 0x038 592#define PCIX0_INTLN 0x03c 593#define PCIX0_INTPN 0x03d 594#define PCIX0_MINGNT 0x03e 595#define PCIX0_MAXLTNCY 0x03f 596#define PCIX0_BRDGOPT1 0x040 597#define PCIX0_BRDGOPT2 0x044 598#define PCIX0_ERREN 0x050 599#define PCIX0_ERRSTS 0x054 600#define PCIX0_PLBBESR 0x058 601#define PCIX0_PLBBEARL 0x05c 602#define PCIX0_PLBBEARH 0x060 603#define PCIX0_POM0LAL 0x068 604#define PCIX0_POM0LAH 0x06c 605#define PCIX0_POM0SA 0x070 606#define PCIX0_POM0PCIAL 0x074 607#define PCIX0_POM0PCIAH 0x078 608#define PCIX0_POM1LAL 0x07c 609#define PCIX0_POM1LAH 0x080 610#define PCIX0_POM1SA 0x084 611#define PCIX0_POM1PCIAL 0x088 612#define PCIX0_POM1PCIAH 0x08c 613#define PCIX0_POM2SA 0x090 614#define PCIX0_PIM0SAL 0x098 615#define PCIX0_PIM0SA PCIX0_PIM0SAL 616#define PCIX0_PIM0LAL 0x09c 617#define PCIX0_PIM0LAH 0x0a0 618#define PCIX0_PIM1SA 0x0a4 619#define PCIX0_PIM1LAL 0x0a8 620#define PCIX0_PIM1LAH 0x0ac 621#define PCIX0_PIM2SAL 0x0b0 622#define PCIX0_PIM2SA PCIX0_PIM2SAL 623#define PCIX0_PIM2LAL 0x0b4 624#define PCIX0_PIM2LAH 0x0b8 625#define PCIX0_OMCAPID 0x0c0 626#define PCIX0_OMNIPTR 0x0c1 627#define PCIX0_OMMC 0x0c2 628#define PCIX0_OMMA 0x0c4 629#define PCIX0_OMMUA 0x0c8 630#define PCIX0_OMMDATA 0x0cc 631#define PCIX0_OMMEOI 0x0ce 632#define PCIX0_PMCAPID 0x0d0 633#define PCIX0_PMNIPTR 0x0d1 634#define PCIX0_PMC 0x0d2 635#define PCIX0_PMCSR 0x0d4 636#define PCIX0_PMCSRBSE 0x0d6 637#define PCIX0_PMDATA 0x0d7 638#define PCIX0_PMSCRR 0x0d8 639#define PCIX0_CAPID 0x0dc 640#define PCIX0_NIPTR 0x0dd 641#define PCIX0_CMD 0x0de 642#define PCIX0_STS 0x0e0 643#define PCIX0_IDR 0x0e4 644#define PCIX0_CID 0x0e8 645#define PCIX0_RID 0x0ec 646#define PCIX0_PIM0SAH 0x0f8 647#define PCIX0_PIM2SAH 0x0fc 648#define PCIX0_MSGIL 0x100 649#define PCIX0_MSGIH 0x104 650#define PCIX0_MSGOL 0x108 651#define PCIX0_MSGOH 0x10c 652#define PCIX0_IM 0x1f8 653 654#define IIC_OWN 0x55 655#define IIC_CLOCK 50 656 657#undef NR_UICS 658#if defined(CONFIG_440GX) 659#define NR_UICS 3 660#elif defined(CONFIG_440SPE) 661#define NR_UICS 4 662#else 663#define NR_UICS 2 664#endif 665 666#include <asm/ibm4xx.h> 667 668#endif /* __ASSEMBLY__ */ 669#endif /* __ASM_IBM44x_H__ */ 670#endif /* __KERNEL__ */ 671