1/*----------------------------------------------------------------------------+ 2| This source code has been made available to you by IBM on an AS-IS 3| basis. Anyone receiving this source is licensed under IBM 4| copyrights to use it in any way he or she deems fit, including 5| copying it, modifying it, compiling it, and redistributing it either 6| with or without modifications. No license under IBM patents or 7| patent applications is to be implied by the copyright license. 8| 9| Any user of this software should understand that IBM cannot provide 10| technical support for this software and will not be responsible for 11| any consequences resulting from the use of this software. 12| 13| Any person who transfers this source code or any derivative work 14| must include the IBM copyright notice, this paragraph, and the 15| preceding two paragraphs in the transferred software. 16| 17| COPYRIGHT I B M CORPORATION 1997 18| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M 19+----------------------------------------------------------------------------*/ 20/*----------------------------------------------------------------------------+ 21| Author: Tony J. Cerreto 22| Component: BSPS 23| File: init_brd.s 24| Purpose: Vesta Evaluation Board initialization subroutines. The following 25| routines are available: 26| 1. INITB_EBIU0: Initialize EBIU0. 27| 2. INITB_CONFIG: Configure board. 28| 3. INITB_HSMC0: Initialize HSMC0 (SDRAM). 29| 4. INITB_HSMC1: Initialize HSMC1 (SDRAM). 30| 5. INITB_CACHE: Initialize Data and Instruction Cache. 31| 6. INITB_DCACHE: Initialize Data Cache. 32| 7. INITB_ICACHE: Initialize Instruction Cache. 33| 8. INITB_GET_CSPD: Get CPU Speed (Bus Speed and Processor Speed) 34| 35| Changes: 36| Date: Author Comment: 37| --------- ------ -------- 38| 01-Mar-00 tjc Created 39| 04-Mar-00 jfh Modified CIC_SEL3_VAL to support 1284 (Mux3 & GPIO 21-28) 40| 04-Mar-00 jfh Modified XILINIX Reg 0 to support 1284 (Mux3 & GPIO 21-28) 41| 04-Mar-00 jfh Modified XILINIX Reg 1 to support 1284 (Mux3 & GPIO 21-28) 42| 04-Mar-00 jfh Modified XILINIX Reg 4 to support 1284 (Mux3 & GPIO 21-28) 43| 19-May-00 rlb Relcoated HSMC0 to 0x1F000000 to support 32MB of contiguous 44| SDRAM space. Changed cache ctl regs to reflect this. 45| 22-May-00 tjc Changed initb_get_cspd interface and eliminated 46| initb_get_bspd routines. 47| 26-May-00 tjc Added two nop instructions after all mtxxx/mfxxx 48| instructions due to PPC405 bug. 49+----------------------------------------------------------------------------*/ 50#define VESTA 51#include "ppc_40x.h" 52#include "stb.h" 53 54/*----------------------------------------------------------------------------+ 55| BOARD CONFIGURATION DEFINES 56+----------------------------------------------------------------------------*/ 57#define CBS0_CR_VAL 0x00000002 /* CBS control reg value */ 58#define CIC0_CR_VAL 0xD0800448 /* CIC control reg value */ 59#define CIC0_SEL3_VAL 0x11500000 /* CIC select 3 reg value */ 60#define CIC0_VCR_VAL 0x00631700 /* CIC video cntl reg value */ 61 62/*----------------------------------------------------------------------------+ 63| EBIU0 BANK REGISTERS DEFINES 64+----------------------------------------------------------------------------*/ 65#define EBIU0_BRCRH0_VAL 0x00000000 /* BR High 0 (Extension Reg)*/ 66#define EBIU0_BRCRH1_VAL 0x00000000 /* BR High 1 (Extension Reg)*/ 67#define EBIU0_BRCRH2_VAL 0x40000000 /* BR High 2 (Extension Reg)*/ 68#define EBIU0_BRCRH3_VAL 0x40000000 /* BR High 3 (Extension Reg)*/ 69#define EBIU0_BRCRH4_VAL 0x00000000 /* BR High 4 (Extension Reg)*/ 70#define EBIU0_BRCRH5_VAL 0x00000000 /* BR High 5 (Extension Reg)*/ 71#define EBIU0_BRCRH6_VAL 0x00000000 /* BR High 6 (Extension Reg)*/ 72#define EBIU0_BRCRH7_VAL 0x40000000 /* BR High 7 (Extension Reg)*/ 73 74#define EBIU0_BRCR0_VAL 0xFC58BFFE /* BR 0: 16 bit Flash 4 MB */ 75#define EBIU0_BRCR1_VAL 0xFF00BFFE /* BR 1: Ext Connector 1 MB */ 76#define EBIU0_BRCR2_VAL 0x207CFFBE /* BR 2: Xilinx 8 MB */ 77 /* twt == 0x3f */ 78#define EBIU0_BRCR3_VAL 0x407CBFBE /* BR 3: IDE Drive 8 MB */ 79#define EBIU0_BRCR4_VAL 0xFF00BFFF /* BR 4: Disabled. 0 MB */ 80#define EBIU0_BRCR5_VAL 0xFF00BFFF /* BR 5: Disabled. 0 MB */ 81#define EBIU0_BRCR6_VAL 0xFF00BFFF /* BR 6: Disabled. 0 MB */ 82#define EBIU0_BRCR7_VAL 0xCE3F0003 /* BR 7: Line Mode DMA 2 MB */ 83 84/*----------------------------------------------------------------------------+ 85| GPIO DEFINES 86+----------------------------------------------------------------------------*/ 87#define STB_GPIO0_OUTPUT (STB_GPIO0_BASE_ADDRESS+ 0x00) 88#define STB_GPIO0_TC (STB_GPIO0_BASE_ADDRESS+ 0x04) 89#define STB_GPIO0_OS_0_31 (STB_GPIO0_BASE_ADDRESS+ 0x08) 90#define STB_GPIO0_OS_32_63 (STB_GPIO0_BASE_ADDRESS+ 0x0C) 91#define STB_GPIO0_TS_0_31 (STB_GPIO0_BASE_ADDRESS+ 0x10) 92#define STB_GPIO0_TS_32_63 (STB_GPIO0_BASE_ADDRESS+ 0x14) 93#define STB_GPIO0_OD (STB_GPIO0_BASE_ADDRESS+ 0x18) 94#define STB_GPIO0_INPUT (STB_GPIO0_BASE_ADDRESS+ 0x1C) 95#define STB_GPIO0_R1 (STB_GPIO0_BASE_ADDRESS+ 0x20) 96#define STB_GPIO0_R2 (STB_GPIO0_BASE_ADDRESS+ 0x24) 97#define STB_GPIO0_R3 (STB_GPIO0_BASE_ADDRESS+ 0x28) 98#define STB_GPIO0_IS_1_0_31 (STB_GPIO0_BASE_ADDRESS+ 0x30) 99#define STB_GPIO0_IS_1_32_63 (STB_GPIO0_BASE_ADDRESS+ 0x34) 100#define STB_GPIO0_IS_2_0_31 (STB_GPIO0_BASE_ADDRESS+ 0x38) 101#define STB_GPIO0_IS_2_32_63 (STB_GPIO0_BASE_ADDRESS+ 0x3C) 102#define STB_GPIO0_IS_3_0_31 (STB_GPIO0_BASE_ADDRESS+ 0x40) 103#define STB_GPIO0_IS_3_32_63 (STB_GPIO0_BASE_ADDRESS+ 0x44) 104#define STB_GPIO0_SS_1 (STB_GPIO0_BASE_ADDRESS+ 0x50) 105#define STB_GPIO0_SS_2 (STB_GPIO0_BASE_ADDRESS+ 0x54) 106#define STB_GPIO0_SS_3 (STB_GPIO0_BASE_ADDRESS+ 0x58) 107 108#define GPIO0_TC_VAL 0x0C020004 /* three-state control val */ 109#define GPIO0_OS_0_31_VAL 0x51A00004 /* output select 0-31 val */ 110#define GPIO0_OS_32_63_VAL 0x0000002F /* output select 32-63 val */ 111#define GPIO0_TS_0_31_VAL 0x51A00000 /* three-state sel 0-31 val*/ 112#define GPIO0_TS_32_63_VAL 0x0000000F /* three-state sel 32-63 val*/ 113#define GPIO0_OD_VAL 0xC0000004 /* open drain val */ 114#define GPIO0_IS_1_0_31_VAL 0x50000151 /* input select 1 0-31 val */ 115#define GPIO0_IS_1_32_63_VAL 0x00000000 /* input select 1 32-63 val */ 116#define GPIO0_IS_2_0_31_VAL 0x00000000 /* input select 2 0-31 val */ 117#define GPIO0_IS_2_32_63_VAL 0x00000000 /* input select 2 32-63 val */ 118#define GPIO0_IS_3_0_31_VAL 0x00000440 /* input select 3 0-31 val */ 119#define GPIO0_IS_3_32_63_VAL 0x00000000 /* input select 3 32-63 val */ 120#define GPIO0_SS_1_VAL 0x00000000 /* sync select 1 val */ 121#define GPIO0_SS_2_VAL 0x00000000 /* sync select 2 val */ 122#define GPIO0_SS_3_VAL 0x00000000 /* sync select 3 val */ 123 124/*----------------------------------------------------------------------------+ 125| XILINX DEFINES 126+----------------------------------------------------------------------------*/ 127#define STB_XILINX_LED (STB_FPGA_BASE_ADDRESS+ 0x0100) 128#define STB_XILINX1_REG0 (STB_FPGA_BASE_ADDRESS+ 0x40000) 129#define STB_XILINX1_REG1 (STB_FPGA_BASE_ADDRESS+ 0x40002) 130#define STB_XILINX1_REG2 (STB_FPGA_BASE_ADDRESS+ 0x40004) 131#define STB_XILINX1_REG3 (STB_FPGA_BASE_ADDRESS+ 0x40006) 132#define STB_XILINX1_REG4 (STB_FPGA_BASE_ADDRESS+ 0x40008) 133#define STB_XILINX1_REG5 (STB_FPGA_BASE_ADDRESS+ 0x4000A) 134#define STB_XILINX1_REG6 (STB_FPGA_BASE_ADDRESS+ 0x4000C) 135#define STB_XILINX1_ID (STB_FPGA_BASE_ADDRESS+ 0x4000E) 136#define STB_XILINX1_FLUSH (STB_FPGA_BASE_ADDRESS+ 0x4000E) 137#define STB_XILINX2_REG0 (STB_FPGA_BASE_ADDRESS+ 0x80000) 138#define STB_XILINX2_REG1 (STB_FPGA_BASE_ADDRESS+ 0x80002) 139#define STB_XILINX2_REG2 (STB_FPGA_BASE_ADDRESS+ 0x80004) 140 141#define XILINX1_R0_VAL 0x2440 /* Xilinx 1 Register 0 Val */ 142#define XILINX1_R1_VAL 0x0025 /* Xilinx 1 Register 1 Val */ 143#define XILINX1_R2_VAL 0x0441 /* Xilinx 1 Register 2 Val */ 144#define XILINX1_R3_VAL 0x0008 /* Xilinx 1 Register 3 Val */ 145#define XILINX1_R4_VAL 0x0100 /* Xilinx 1 Register 4 Val */ 146#define XILINX1_R5_VAL 0x6810 /* Xilinx 1 Register 5 Val */ 147#define XILINX1_R6_VAL 0x0000 /* Xilinx 1 Register 6 Val */ 148#define XILINX2_R0_VAL 0x0018 /* disable IBM IrDA RxD */ 149#define XILINX2_R1_VAL 0x0008 /* enable SICC MAX chip */ 150#define XILINX2_R2_VAL 0x0000 /* Xilinx 2 Register 2 Val */ 151 152/*----------------------------------------------------------------------------+ 153| HSMC BANK REGISTERS DEFINES 154+----------------------------------------------------------------------------*/ 155#ifdef SDRAM16MB 156#define HSMC0_BR0_VAL 0x000D2D55 /* 0x1F000000-007FFFFF R/W */ 157#define HSMC0_BR1_VAL 0x008D2D55 /* 0x1F800000-1FFFFFFF R/W */ 158#else 159#define HSMC0_BR0_VAL 0x1F0D2D55 /* 0x1F000000-007FFFFF R/W */ 160#define HSMC0_BR1_VAL 0x1F8D2D55 /* 0x1F800000-1FFFFFFF R/W */ 161#endif 162#define HSMC1_BR0_VAL 0xA00D2D55 /* 0xA0000000-A07FFFFF R/W */ 163#define HSMC1_BR1_VAL 0xA08D2D55 /* 0xA0800000-A0FFFFFF R/W */ 164 165/*----------------------------------------------------------------------------+ 166| CACHE DEFINES 167+----------------------------------------------------------------------------*/ 168#define DCACHE_NLINES 128 /* no. D-cache lines */ 169#define DCACHE_NBYTES 32 /* no. bytes/ D-cache line */ 170#define ICACHE_NLINES 256 /* no. I-cache lines */ 171#define ICACHE_NBYTES 32 /* no. bytes/ I-cache line */ 172#ifdef SDRAM16MB 173#define DCACHE_ENABLE 0x80000000 /* D-cache regions to enable*/ 174#define ICACHE_ENABLE 0x80000001 /* I-cache regions to enable*/ 175#else 176#define DCACHE_ENABLE 0x18000000 /* D-cache regions to enable*/ 177#define ICACHE_ENABLE 0x18000001 /* I-cache regions to enable*/ 178#endif 179 180/*----------------------------------------------------------------------------+ 181| CPU CORE SPEED CALCULATION DEFINES 182+----------------------------------------------------------------------------*/ 183#define GCS_LCNT 500000 /* CPU speed loop count */ 184#define GCS_TROW_BYTES 8 /* no. bytes in table row */ 185#define GCS_CTICK_TOL 100 /* allowable clock tick tol */ 186#define GCS_NMULT 4 /* no. of core speed mults */ 187 188 /*--------------------------------------------------------------------+ 189 | No. 13.5Mhz 190 | Clock Ticks 191 | based on a 192 | loop count Bus 193 | of 100,000 Speed 194 +--------------------------------------------------------------------*/ 195gcs_lookup_table: 196 .int 50000, 54000000 /* 54.0 Mhz */ 197 .int 66667, 40500000 /* 40.5 Mhz */ 198 .int 54545, 49500000 /* 49.5 Mhz */ 199 .int 46154, 58500000 /* 58.5 Mhz */ 200 .int 0, 0 /* end of table flag */ 201 202 203/****************************************************************************** 204| 205| Routine: INITB_EBIU0. 206| 207| Purpose: Initialize all the EBIU0 Bank Registers 208| Parameters: None. 209| Returns: None. 210| 211******************************************************************************/ 212 function_prolog(initb_ebiu0) 213 /*--------------------------------------------------------------------+ 214 | Set EBIU0 Bank 0 215 +--------------------------------------------------------------------*/ 216 lis r10,EBIU0_BRCR0_VAL@h 217 ori r10,r10,EBIU0_BRCR0_VAL@l 218 mtdcr ebiu0_brcr0,r10 219 lis r10,EBIU0_BRCRH0_VAL@h 220 ori r10,r10,EBIU0_BRCRH0_VAL@l 221 mtdcr ebiu0_brcrh0,r10 222 223 /*--------------------------------------------------------------------+ 224 | Set EBIU0 Bank 1 225 +--------------------------------------------------------------------*/ 226 lis r10,EBIU0_BRCR1_VAL@h 227 ori r10,r10,EBIU0_BRCR1_VAL@l 228 mtdcr ebiu0_brcr1,r10 229 lis r10,EBIU0_BRCRH1_VAL@h 230 ori r10,r10,EBIU0_BRCRH1_VAL@l 231 mtdcr ebiu0_brcrh1,r10 232 233 /*--------------------------------------------------------------------+ 234 | Set EBIU0 Bank 2 235 +--------------------------------------------------------------------*/ 236 lis r10,EBIU0_BRCR2_VAL@h 237 ori r10,r10,EBIU0_BRCR2_VAL@l 238 mtdcr ebiu0_brcr2,r10 239 lis r10,EBIU0_BRCRH2_VAL@h 240 ori r10,r10,EBIU0_BRCRH2_VAL@l 241 mtdcr ebiu0_brcrh2,r10 242 243 /*--------------------------------------------------------------------+ 244 | Set EBIU0 Bank 3 245 +--------------------------------------------------------------------*/ 246 lis r10,EBIU0_BRCR3_VAL@h 247 ori r10,r10,EBIU0_BRCR3_VAL@l 248 mtdcr ebiu0_brcr3,r10 249 lis r10,EBIU0_BRCRH3_VAL@h 250 ori r10,r10,EBIU0_BRCRH3_VAL@l 251 mtdcr ebiu0_brcrh3,r10 252 253 /*--------------------------------------------------------------------+ 254 | Set EBIU0 Bank 4 255 +--------------------------------------------------------------------*/ 256 lis r10,EBIU0_BRCR4_VAL@h 257 ori r10,r10,EBIU0_BRCR4_VAL@l 258 mtdcr ebiu0_brcr4,r10 259 lis r10,EBIU0_BRCRH4_VAL@h 260 ori r10,r10,EBIU0_BRCRH4_VAL@l 261 mtdcr ebiu0_brcrh4,r10 262 263 /*--------------------------------------------------------------------+ 264 | Set EBIU0 Bank 5 265 +--------------------------------------------------------------------*/ 266 lis r10,EBIU0_BRCR5_VAL@h 267 ori r10,r10,EBIU0_BRCR5_VAL@l 268 mtdcr ebiu0_brcr5,r10 269 lis r10,EBIU0_BRCRH5_VAL@h 270 ori r10,r10,EBIU0_BRCRH5_VAL@l 271 mtdcr ebiu0_brcrh5,r10 272 273 /*--------------------------------------------------------------------+ 274 | Set EBIU0 Bank 6 275 +--------------------------------------------------------------------*/ 276 lis r10,EBIU0_BRCR6_VAL@h 277 ori r10,r10,EBIU0_BRCR6_VAL@l 278 mtdcr ebiu0_brcr6,r10 279 lis r10,EBIU0_BRCRH6_VAL@h 280 ori r10,r10,EBIU0_BRCRH6_VAL@l 281 mtdcr ebiu0_brcrh6,r10 282 283 /*--------------------------------------------------------------------+ 284 | Set EBIU0 Bank 7 285 +--------------------------------------------------------------------*/ 286 lis r10,EBIU0_BRCR7_VAL@h 287 ori r10,r10,EBIU0_BRCR7_VAL@l 288 mtdcr ebiu0_brcr7,r10 289 lis r10,EBIU0_BRCRH7_VAL@h 290 ori r10,r10,EBIU0_BRCRH7_VAL@l 291 mtdcr ebiu0_brcrh7,r10 292 293 blr 294 function_epilog(initb_ebiu0) 295 296 297/****************************************************************************** 298| 299| Routine: INITB_CONFIG 300| 301| Purpose: Configure the Vesta Evaluation Board. The following items 302| will be configured: 303| 1. Cross-Bar Switch. 304| 2. Chip Interconnect. 305| 3. Clear/reset key PPC registers. 306| 4. Xilinx and GPIO Registers. 307| 308| Returns: None. 309| 310******************************************************************************/ 311 function_prolog(initb_config) 312 /*--------------------------------------------------------------------+ 313 | Init CROSS-BAR SWITCH 314 +--------------------------------------------------------------------*/ 315 lis r10,CBS0_CR_VAL@h /* r10 <- CBS Cntl Reg val */ 316 ori r10,r10,CBS0_CR_VAL@l 317 mtdcr cbs0_cr,r10 318 319 /*--------------------------------------------------------------------+ 320 | Init Chip-Interconnect (CIC) Registers 321 +--------------------------------------------------------------------*/ 322 lis r10,CIC0_CR_VAL@h /* r10 <- CIC Cntl Reg val */ 323 ori r10,r10,CIC0_CR_VAL@l 324 mtdcr cic0_cr,r10 325 326 lis r10,CIC0_SEL3_VAL@h /* r10 <- CIC SEL3 Reg val */ 327 ori r10,r10,CIC0_SEL3_VAL@l 328 mtdcr cic0_sel3,r10 329 330 lis r10,CIC0_VCR_VAL@h /* r10 <- CIC Vid C-Reg val */ 331 ori r10,r10,CIC0_VCR_VAL@l 332 mtdcr cic0_vcr,r10 333 334 /*--------------------------------------------------------------------+ 335 | Clear SGR and DCWR 336 +--------------------------------------------------------------------*/ 337 li r10,0x0000 338 mtspr sgr,r10 339 mtspr dcwr,r10 340 341 /*--------------------------------------------------------------------+ 342 | Clear/set up some machine state registers. 343 +--------------------------------------------------------------------*/ 344 li r10,0x0000 /* r10 <- 0 */ 345 mtdcr ebiu0_besr,r10 /* clr Bus Err Syndrome Reg */ 346 mtspr esr,r10 /* clr Exceptn Syndrome Reg */ 347 mttcr r10 /* timer control register */ 348 349 mtdcr uic0_er,r10 /* disable all interrupts */ 350 351 /* UIC_IIC0 | UIC_IIC1 | UIC_U0 | UIC_IR_RCV | UIC_IR_XMIT */ 352 lis r10, 0x00600e00@h 353 ori r10,r10,0x00600e00@l 354 mtdcr uic0_pr,r10 355 356 li r10,0x00000020 /* UIC_EIR1 */ 357 mtdcr uic0_tr,r10 358 359 lis r10,0xFFFF /* r10 <- 0xFFFFFFFF */ 360 ori r10,r10,0xFFFF /* */ 361 mtdbsr r10 /* clear/reset the dbsr */ 362 mtdcr uic0_sr,r10 /* clear pending interrupts */ 363 364 li r10,0x1000 /* set Machine Exception bit*/ 365 oris r10,r10,0x2 /* set Criticl Exception bit*/ 366 mtmsr r10 /* change MSR */ 367 368 /*--------------------------------------------------------------------+ 369 | Clear XER. 370 +--------------------------------------------------------------------*/ 371 li r10,0x0000 372 mtxer r10 373 374 /*--------------------------------------------------------------------+ 375 | Init GPIO0 Registers 376 +--------------------------------------------------------------------*/ 377 lis r10, STB_GPIO0_TC@h /* Three-state control */ 378 ori r10,r10,STB_GPIO0_TC@l 379 lis r11, GPIO0_TC_VAL@h 380 ori r11,r11,GPIO0_TC_VAL@l 381 stw r11,0(r10) 382 383 lis r10, STB_GPIO0_OS_0_31@h /* output select 0-31 */ 384 ori r10,r10,STB_GPIO0_OS_0_31@l 385 lis r11, GPIO0_OS_0_31_VAL@h 386 ori r11,r11,GPIO0_OS_0_31_VAL@l 387 stw r11,0(r10) 388 389 lis r10, STB_GPIO0_OS_32_63@h /* output select 32-63 */ 390 ori r10,r10,STB_GPIO0_OS_32_63@l 391 lis r11, GPIO0_OS_32_63_VAL@h 392 ori r11,r11,GPIO0_OS_32_63_VAL@l 393 stw r11,0(r10) 394 395 lis r10, STB_GPIO0_TS_0_31@h /* three-state select 0-31 */ 396 ori r10,r10,STB_GPIO0_TS_0_31@l 397 lis r11, GPIO0_TS_0_31_VAL@h 398 ori r11,r11,GPIO0_TS_0_31_VAL@l 399 stw r11,0(r10) 400 401 lis r10, STB_GPIO0_TS_32_63@h /* three-state select 32-63 */ 402 ori r10,r10,STB_GPIO0_TS_32_63@l 403 lis r11, GPIO0_TS_32_63_VAL@h 404 ori r11,r11,GPIO0_TS_32_63_VAL@l 405 stw r11,0(r10) 406 407 lis r10, STB_GPIO0_OD@h /* open drain */ 408 ori r10,r10,STB_GPIO0_OD@l 409 lis r11, GPIO0_OD_VAL@h 410 ori r11,r11,GPIO0_OD_VAL@l 411 stw r11,0(r10) 412 413 lis r10, STB_GPIO0_IS_1_0_31@h /* input select 1, 0-31 */ 414 ori r10,r10,STB_GPIO0_IS_1_0_31@l 415 lis r11, GPIO0_IS_1_0_31_VAL@h 416 ori r11,r11,GPIO0_IS_1_0_31_VAL@l 417 stw r11,0(r10) 418 419 lis r10, STB_GPIO0_IS_1_32_63@h /* input select 1, 32-63 */ 420 ori r10,r10,STB_GPIO0_IS_1_32_63@l 421 lis r11, GPIO0_IS_1_32_63_VAL@h 422 ori r11,r11,GPIO0_IS_1_32_63_VAL@l 423 stw r11,0(r10) 424 425 lis r10, STB_GPIO0_IS_2_0_31@h /* input select 2, 0-31 */ 426 ori r10,r10,STB_GPIO0_IS_2_0_31@l 427 lis r11, GPIO0_IS_2_0_31_VAL@h 428 ori r11,r11,GPIO0_IS_2_0_31_VAL@l 429 stw r11,0(r10) 430 431 lis r10, STB_GPIO0_IS_2_32_63@h /* input select 2, 32-63 */ 432 ori r10,r10,STB_GPIO0_IS_2_32_63@l 433 lis r11, GPIO0_IS_2_32_63_VAL@h 434 ori r11,r11,GPIO0_IS_2_32_63_VAL@l 435 stw r11,0(r10) 436 437 lis r10, STB_GPIO0_IS_3_0_31@h /* input select 3, 0-31 */ 438 ori r10,r10,STB_GPIO0_IS_3_0_31@l 439 lis r11, GPIO0_IS_3_0_31_VAL@h 440 ori r11,r11,GPIO0_IS_3_0_31_VAL@l 441 stw r11,0(r10) 442 443 lis r10, STB_GPIO0_IS_3_32_63@h /* input select 3, 32-63 */ 444 ori r10,r10,STB_GPIO0_IS_3_32_63@l 445 lis r11, GPIO0_IS_3_32_63_VAL@h 446 ori r11,r11,GPIO0_IS_3_32_63_VAL@l 447 stw r11,0(r10) 448 449 lis r10, STB_GPIO0_SS_1@h /* sync select 1 */ 450 ori r10,r10,STB_GPIO0_SS_1@l 451 lis r11, GPIO0_SS_1_VAL@h 452 ori r11,r11,GPIO0_SS_1_VAL@l 453 stw r11,0(r10) 454 455 lis r10, STB_GPIO0_SS_2@h /* sync select 2 */ 456 ori r10,r10,STB_GPIO0_SS_2@l 457 lis r11, GPIO0_SS_2_VAL@h 458 ori r11,r11,GPIO0_SS_2_VAL@l 459 stw r11,0(r10) 460 461 lis r10, STB_GPIO0_SS_3@h /* sync select 3 */ 462 ori r10,r10,STB_GPIO0_SS_3@l 463 lis r11, GPIO0_SS_3_VAL@h 464 ori r11,r11,GPIO0_SS_3_VAL@l 465 stw r11,0(r10) 466 467 /*--------------------------------------------------------------------+ 468 | Init Xilinx #1 Registers 469 +--------------------------------------------------------------------*/ 470 lis r10, STB_XILINX1_REG0@h /* init Xilinx1 Reg 0 */ 471 ori r10,r10,STB_XILINX1_REG0@l 472 li r11,XILINX1_R0_VAL 473 sth r11,0(r10) 474 475 lis r10, STB_XILINX1_REG1@h /* init Xilinx1 Reg 1 */ 476 ori r10,r10,STB_XILINX1_REG1@l 477 li r11,XILINX1_R1_VAL 478 sth r11,0(r10) 479 480 lis r10, STB_XILINX1_REG2@h /* init Xilinx1 Reg 2 */ 481 ori r10,r10,STB_XILINX1_REG2@l 482 li r11,XILINX1_R2_VAL 483 sth r11,0(r10) 484 485 lis r10, STB_XILINX1_REG3@h /* init Xilinx1 Reg 3 */ 486 ori r10,r10,STB_XILINX1_REG3@l 487 li r11,XILINX1_R3_VAL 488 sth r11,0(r10) 489 490 lis r10, STB_XILINX1_REG4@h /* init Xilinx1 Reg 4 */ 491 ori r10,r10,STB_XILINX1_REG4@l 492 li r11,XILINX1_R4_VAL 493 sth r11,0(r10) 494 495 lis r10, STB_XILINX1_REG5@h /* init Xilinx1 Reg 5 */ 496 ori r10,r10,STB_XILINX1_REG5@l 497 li r11,XILINX1_R5_VAL 498 sth r11,0(r10) 499 500 lis r10, STB_XILINX1_REG6@h /* init Xilinx1 Reg 6 */ 501 ori r10,r10,STB_XILINX1_REG6@l 502 li r11,XILINX1_R6_VAL 503 sth r11,0(r10) 504 505 lis r10, STB_XILINX1_FLUSH@h /* latch registers in Xilinx*/ 506 ori r10,r10,STB_XILINX1_FLUSH@l 507 li r11,0x0000 508 sth r11,0(r10) 509 510 /*--------------------------------------------------------------------+ 511 | Init Xilinx #2 Registers 512 +--------------------------------------------------------------------*/ 513 lis r10, STB_XILINX2_REG0@h /* init Xilinx2 Reg 0 */ 514 ori r10,r10,STB_XILINX2_REG0@l 515 li r11,XILINX2_R0_VAL 516 sth r11,0(r10) 517 518 lis r10, STB_XILINX2_REG1@h /* init Xilinx2 Reg 1 */ 519 ori r10,r10,STB_XILINX2_REG1@l 520 li r11,XILINX2_R1_VAL 521 sth r11,0(r10) 522 523 lis r10, STB_XILINX2_REG2@h /* init Xilinx2 Reg 2 */ 524 ori r10,r10,STB_XILINX2_REG2@l 525 li r11,XILINX2_R2_VAL 526 sth r11,0(r10) 527 528 blr 529 function_epilog(initb_config) 530 531 532/****************************************************************************** 533| 534| Routine: INITB_HSMC0. 535| 536| Purpose: Initialize the HSMC0 Registers for SDRAM 537| Parameters: None. 538| Returns: R3 = 0: Successful 539| = -1: Unsuccessful, SDRAM did not reset properly. 540| 541******************************************************************************/ 542 function_prolog(initb_hsmc0) 543 mflr r0 /* Save return addr */ 544 545 /*--------------------------------------------------------------------+ 546 | Set Global SDRAM Controller to recommended default 547 +--------------------------------------------------------------------*/ 548 lis r10,0x6C00 549 ori r10,r10,0x0000 550 mtdcr hsmc0_gr,r10 551 552 /*--------------------------------------------------------------------+ 553 | Set HSMC0 Data Register to recommended default 554 +--------------------------------------------------------------------*/ 555 lis r10,0x0037 556 ori r10,r10,0x0000 557 mtdcr hsmc0_data,r10 558 559 /*--------------------------------------------------------------------+ 560 | Init HSMC0 Bank Register 0 561 +--------------------------------------------------------------------*/ 562 lis r10,HSMC0_BR0_VAL@h 563 ori r10,r10,HSMC0_BR0_VAL@l 564 mtdcr hsmc0_br0,r10 565 566 /*--------------------------------------------------------------------+ 567 | Init HSMC0 Bank Register 1 568 +--------------------------------------------------------------------*/ 569 lis r10,HSMC0_BR1_VAL@h 570 ori r10,r10,HSMC0_BR1_VAL@l 571 mtdcr hsmc0_br1,r10 572 573 /*--------------------------------------------------------------------+ 574 | Set HSMC0 Control Reg 0 575 +--------------------------------------------------------------------*/ 576 lis r10,0x8077 /* PRECHARGE ALL DEVICE BKS */ 577 ori r10,r10,0x0000 578 mtdcr hsmc0_cr0,r10 579 li r3,0x0000 580 bl hsmc_cr_wait /* wait for op completion */ 581 cmpwi cr0,r3,0x0000 582 bne cr0,hsmc0_err 583 584 lis r10,0x8078 /* AUTO-REFRESH */ 585 ori r10,r10,0x0000 586 mtdcr hsmc0_cr0,r10 587 li r3,0x0000 588 bl hsmc_cr_wait /* wait for op completion */ 589 cmpwi cr0,r3,0x0000 590 bne cr0,hsmc0_err 591 592 lis r10,0x8070 /* PROG MODE W/DATA REG VAL */ 593 ori r10,r10,0x8000 594 mtdcr hsmc0_cr0,r10 595 li r3,0x0000 596 bl hsmc_cr_wait /* wait for op completion */ 597 cmpwi cr0,r3,0x0000 598 bne hsmc0_err 599 600 /*--------------------------------------------------------------------+ 601 | Set HSMC0 Control Reg 1 602 +--------------------------------------------------------------------*/ 603 lis r10,0x8077 /* PRECHARGE ALL DEVICE BKS */ 604 ori r10,r10,0x0000 605 mtdcr hsmc0_cr1,r10 606 li r3,0x0001 607 bl hsmc_cr_wait /* wait for op completion */ 608 cmpwi cr0,r3,0x0000 609 bne cr0,hsmc0_err 610 611 lis r10,0x8078 /* AUTO-REFRESH */ 612 ori r10,r10,0x0000 613 mtdcr hsmc0_cr1,r10 614 li r3,0x0001 615 bl hsmc_cr_wait /* wait for op completion */ 616 cmpwi cr0,r3,0x0000 617 bne cr0,hsmc0_err 618 619 lis r10,0x8070 /* PROG MODE W/DATA REG VAL */ 620 ori r10,r10,0x8000 621 mtdcr hsmc0_cr1,r10 622 li r3,0x0001 623 bl hsmc_cr_wait /* wait for op completion */ 624 cmpwi cr0,r3,0x0000 625 bne cr0,hsmc0_err 626 627 /*--------------------------------------------------------------------+ 628 | Set HSMC0 Refresh Register 629 +--------------------------------------------------------------------*/ 630 lis r10,0x0FE1 631 ori r10,r10,0x0000 632 mtdcr hsmc0_crr,r10 633 li r3,0 634 635hsmc0_err: 636 mtlr r0 637 blr 638 function_epilog(initb_hsmc0) 639 640 641/****************************************************************************** 642| 643| Routine: INITB_HSMC1. 644| 645| Purpose: Initialize the HSMC1 Registers for SDRAM 646| Parameters: None. 647| Returns: R3 = 0: Successful 648| = -1: Unsuccessful, SDRAM did not reset properly. 649| 650******************************************************************************/ 651 function_prolog(initb_hsmc1) 652 mflr r0 /* Save return addr */ 653 654 /*--------------------------------------------------------------------+ 655 | Set Global SDRAM Controller to recommended default 656 +--------------------------------------------------------------------*/ 657 lis r10,0x6C00 658 ori r10,r10,0x0000 659 mtdcr hsmc1_gr,r10 660 661 /*--------------------------------------------------------------------+ 662 | Set HSMC1 Data Register to recommended default 663 +--------------------------------------------------------------------*/ 664 lis r10,0x0037 665 ori r10,r10,0x0000 666 mtdcr hsmc1_data,r10 667 668 /*--------------------------------------------------------------------+ 669 | Init HSMC1 Bank Register 0 670 +--------------------------------------------------------------------*/ 671 lis r10,HSMC1_BR0_VAL@h 672 ori r10,r10,HSMC1_BR0_VAL@l 673 mtdcr hsmc1_br0,r10 674 675 /*--------------------------------------------------------------------+ 676 | Init HSMC1 Bank Register 1 677 +--------------------------------------------------------------------*/ 678 lis r10,HSMC1_BR1_VAL@h 679 ori r10,r10,HSMC1_BR1_VAL@l 680 mtdcr hsmc1_br1,r10 681 682 /*--------------------------------------------------------------------+ 683 | Set HSMC1 Control Reg 0 684 +--------------------------------------------------------------------*/ 685 lis r10,0x8077 /* PRECHARGE ALL DEVICE BANKS */ 686 ori r10,r10,0x0000 687 mtdcr hsmc1_cr0,r10 688 li r3,0x0002 689 bl hsmc_cr_wait /* wait for operation completion */ 690 cmpwi cr0,r3,0x0000 691 bne hsmc1_err 692 693 lis r10,0x8078 /* AUTO-REFRESH */ 694 ori r10,r10,0x0000 695 mtdcr hsmc1_cr0,r10 696 li r3,0x0002 697 bl hsmc_cr_wait /* wait for operation completion */ 698 cmpwi cr0,r3,0x0000 699 bne hsmc1_err 700 701 lis r10,0x8070 /* PROGRAM MODE W/DATA REG VALUE */ 702 ori r10,r10,0x8000 703 mtdcr hsmc1_cr0,r10 704 li r3,0x0002 705 bl hsmc_cr_wait /* wait for operation completion */ 706 cmpwi cr0,r3,0x0000 707 bne hsmc1_err 708 709 /*--------------------------------------------------------------------+ 710 | Set HSMC1 Control Reg 1 711 +--------------------------------------------------------------------*/ 712 lis r10,0x8077 /* PRECHARGE ALL DEVICE BKS */ 713 ori r10,r10,0x0000 714 mtdcr hsmc1_cr1,r10 715 li r3,0x0003 716 bl hsmc_cr_wait /* wait for op completion */ 717 cmpwi cr0,r3,0x0000 718 bne hsmc1_err 719 720 lis r10,0x8078 /* AUTO-REFRESH */ 721 ori r10,r10,0x0000 722 mtdcr hsmc1_cr1,r10 723 li r3,0x0003 724 bl hsmc_cr_wait /* wait for op completion */ 725 cmpwi cr0,r3,0x0000 726 bne hsmc1_err 727 728 lis r10,0x8070 /* PROG MODE W/DATA REG VAL */ 729 ori r10,r10,0x8000 730 mtdcr hsmc1_cr1,r10 731 li r3,0x0003 732 bl hsmc_cr_wait /* wait for op completion */ 733 cmpwi cr0,r3,0x0000 734 bne hsmc1_err 735 736 /*--------------------------------------------------------------------+ 737 | Set HSMC1 Refresh Register 738 +--------------------------------------------------------------------*/ 739 lis r10,0x0FE1 740 ori r10,r10,0x0000 741 mtdcr hsmc1_crr,r10 742 xor r3,r3,r3 743 744hsmc1_err: 745 mtlr r0 746 blr 747 function_epilog(initb_hsmc1) 748 749 750/****************************************************************************** 751| 752| Routine: INITB_CACHE 753| 754| Purpose: This routine will enable Data and Instruction Cache. 755| The Data Cache is an 8K two-way set associative and the 756| Instruction Cache is an 16K two-way set associative cache. 757| 758| Parameters: None. 759| 760| Returns: None. 761| 762******************************************************************************/ 763 function_prolog(initb_cache) 764 mflr r0 /* Save return addr */ 765 766 bl initb_Dcache /* enable D-Cache */ 767 bl initb_Icache /* enable I-Cache */ 768 769 mtlr r0 770 blr 771 function_epilog(initb_cache) 772 773 774/****************************************************************************** 775| 776| Routine: INITB_DCACHE 777| 778| Purpose: This routine will invalidate all data in the Data Cache and 779| then enable D-Cache. If cache is enabled already, the D-Cache 780| will be flushed before the data is invalidated. 781| 782| Parameters: None. 783| 784| Returns: None. 785| 786******************************************************************************/ 787 function_prolog(initb_Dcache) 788 /*--------------------------------------------------------------------+ 789 | Flush Data Cache if enabled 790 +--------------------------------------------------------------------*/ 791 mfdccr r10 /* r10 <- DCCR */ 792 isync /* ensure prev insts done */ 793 cmpwi r10,0x00 794 beq ic_dcinv /* D-cache off, invalidate */ 795 796 /*--------------------------------------------------------------------+ 797 | Data Cache enabled, force known memory addresses to be Cached 798 +--------------------------------------------------------------------*/ 799 lis r10,HSMC0_BR0_VAL@h /* r10 <- first memory loc */ 800 andis. r10,r10,0xFFF0 801 li r11,DCACHE_NLINES /* r11 <- # A-way addresses */ 802 addi r11,r11,DCACHE_NLINES /* r11 <- # B-way addresses */ 803 mtctr r11 /* set loop counter */ 804 805ic_dcload: 806 lwz r12,0(r10) /* force cache of address */ 807 addi r10,r10,DCACHE_NBYTES /* r10 <- next memory loc */ 808 bdnz ic_dcload 809 sync /* ensure prev insts done */ 810 isync 811 812 /*--------------------------------------------------------------------+ 813 | Flush the known memory addresses from Cache 814 +--------------------------------------------------------------------*/ 815 lis r10,HSMC0_BR0_VAL@h /* r10 <- first memory loc */ 816 andis. r10,r10,0xFFF0 817 mtctr r11 /* set loop counter */ 818 819ic_dcflush: 820 dcbf 0,r10 /* flush D-cache line */ 821 addi r10,r10,DCACHE_NBYTES /* r10 <- next memory loc */ 822 bdnz ic_dcflush 823 sync /* ensure prev insts done */ 824 isync 825 826 /*--------------------------------------------------------------------+ 827 | Disable then invalidate Data Cache 828 +--------------------------------------------------------------------*/ 829 li r10,0 /* r10 <- 0 */ 830 mtdccr r10 /* disable the D-Cache */ 831 isync /* ensure prev insts done */ 832 833ic_dcinv: 834 li r10,0 /* r10 <- line address */ 835 li r11,DCACHE_NLINES /* r11 <- # lines in cache */ 836 mtctr r11 /* set loop counter */ 837 838ic_dcloop: 839 dccci 0,r10 /* invalidate A/B cache lns */ 840 addi r10,r10,DCACHE_NBYTES /* bump to next line */ 841 bdnz ic_dcloop 842 sync /* ensure prev insts done */ 843 isync 844 845 /*--------------------------------------------------------------------+ 846 | Enable Data Cache 847 +--------------------------------------------------------------------*/ 848 lis r10,DCACHE_ENABLE@h /* r10 <- D-cache enable msk*/ 849 ori r10,r10,DCACHE_ENABLE@l 850 mtdccr r10 851 sync /* ensure prev insts done */ 852 isync 853 854 blr 855 function_epilog(initb_Dcache) 856 857 858/****************************************************************************** 859| 860| Routine: INITB_ICACHE 861| 862| Purpose: This routine will invalidate all data in the Instruction 863| Cache then enable I-Cache. 864| 865| Parameters: None. 866| 867| Returns: None. 868| 869******************************************************************************/ 870 function_prolog(initb_Icache) 871 /*--------------------------------------------------------------------+ 872 | Invalidate Instruction Cache 873 +--------------------------------------------------------------------*/ 874 li r10,0 /* r10 <- lines address */ 875 iccci 0,r10 /* invalidate all I-cache */ 876 sync /* ensure prev insts done */ 877 isync 878 879 /*--------------------------------------------------------------------+ 880 | Enable Instruction Cache 881 +--------------------------------------------------------------------*/ 882 lis r10,ICACHE_ENABLE@h /* r10 <- I-cache enable msk*/ 883 ori r10,r10,ICACHE_ENABLE@l 884 mticcr r10 885 sync /* ensure prev insts done */ 886 isync 887 888 blr 889 function_epilog(initb_Icache) 890 891/****************************************************************************** 892| 893| Routine: HSMC_CR_WAIT 894| 895| Purpose: Wait for the HSMC Control Register (bits 12-16) to be reset 896| after an auto-refresh, pre-charge or program mode register 897| command execution. 898| 899| Parameters: R3 = HSMC Control Register ID. 900| 0: HSMC0 CR0 901| 1: HSMC0 CR1 902| 2: HSMC1 CR0 903| 3: HSMC1 CR1 904| 905| Returns: R3 = 0: Successful 906| -1: Unsuccessful 907| 908******************************************************************************/ 909hsmc_cr_wait: 910 911 li r11,10 /* r11 <- retry counter */ 912 mtctr r11 /* set retry counter */ 913 mr r11,r3 /* r11 <- HSMC CR reg id */ 914 915hsmc_cr_rep: 916 bdz hsmc_cr_err /* branch if max retries hit*/ 917 918 /*--------------------------------------------------------------------+ 919 | GET HSMCx_CRx value based on HSMC Control Register ID 920 +--------------------------------------------------------------------*/ 921try_hsmc0_cr0: /* CHECK IF ID=HSMC0 CR0 REG*/ 922 cmpwi cr0,r11,0x0000 923 bne cr0,try_hsmc0_cr1 924 mfdcr r10,hsmc0_cr0 /* r11 <- HSMC0 CR0 value */ 925 b hsmc_cr_read 926 927try_hsmc0_cr1: /* CHECK IF ID=HSMC0 CR1 REG*/ 928 cmpwi cr0,r11,0x0001 929 bne cr0,try_hsmc1_cr0 930 mfdcr r10,hsmc0_cr1 /* r10 <- HSMC0 CR1 value */ 931 b hsmc_cr_read 932 933try_hsmc1_cr0: /* CHECK IF ID=HSMC1 CR0 REG*/ 934 cmpwi cr0,r11,0x0002 935 bne cr0,try_hsmc1_cr1 936 mfdcr r10,hsmc1_cr0 /* r10 <- HSMC1 CR0 value */ 937 b hsmc_cr_read 938 939try_hsmc1_cr1: /* CHECK IF ID=HSMC1 CR1 REG*/ 940 cmpwi cr0,r11,0x0003 941 bne cr0,hsmc_cr_err 942 mfdcr r10,hsmc1_cr1 /* r10 <- HSMC1 CR1 value */ 943 944 /*--------------------------------------------------------------------+ 945 | Check if HSMC CR register was reset after command execution 946 +--------------------------------------------------------------------*/ 947hsmc_cr_read: 948 lis r12,0x000F /* create "AND" mask */ 949 ori r12,r12,0x8000 950 and. r10,r10,r12 /* r10 <- HSMC CR bits 12-16*/ 951 bne cr0,hsmc_cr_rep /* wait for bits to reset */ 952 li r3,0 /* set return code = success*/ 953 b hsmc_cr_done 954 955hsmc_cr_err: /* ERROR: SDRAM didn't reset*/ 956 li r3,-1 /* set RC=unsuccessful */ 957 958hsmc_cr_done: 959 blr 960