Searched refs:clk_mgr_base (Results 1 - 12 of 12) sorted by relevance

/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dce100/
H A Ddce_clk_mgr.h36 int dce_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base);
38 struct clk_mgr *clk_mgr_base,
53 struct clk_mgr *clk_mgr_base,
H A Damdgpu_dce_clk_mgr.c134 int dce_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base) argument
136 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
160 int dce12_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base) argument
162 struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base);
164 return dce_adjust_dp_ref_freq_for_ss(clk_mgr_dce, clk_mgr_base->dprefclk_khz);
200 struct clk_mgr *clk_mgr_base,
203 struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base);
235 struct clk_mgr *clk_mgr_base,
238 struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base);
240 struct dc_bios *bp = clk_mgr_base
199 dce_get_required_clocks_state( struct clk_mgr *clk_mgr_base, struct dc_state *context) argument
234 dce_set_clock( struct clk_mgr *clk_mgr_base, int requested_clk_khz) argument
400 dce_update_clocks(struct clk_mgr *clk_mgr_base, struct dc_state *context, bool safe_to_lower) argument
[all...]
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dce112/
H A Ddce112_clk_mgr.h37 int dce112_set_clock(struct clk_mgr *clk_mgr_base, int requested_clk_khz);
H A Damdgpu_dce112_clk_mgr.c75 int dce112_set_clock(struct clk_mgr *clk_mgr_base, int requested_clk_khz) argument
77 struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base);
79 struct dc_bios *bp = clk_mgr_base->ctx->dc_bios;
80 struct dc *dc = clk_mgr_base->ctx->dc;
109 if (!ASICREV_IS_VEGA20_P(clk_mgr_base->ctx->asic_id.hw_internal_rev))
198 static void dce112_update_clocks(struct clk_mgr *clk_mgr_base, argument
202 struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base);
210 level_change_req.power_level = dce_get_required_clocks_state(clk_mgr_base, context);
214 if (dm_pp_apply_power_level_change_request(clk_mgr_base->ctx, &level_change_req))
218 if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr_base
[all...]
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dce120/
H A Damdgpu_dce120_clk_mgr.c89 static void dce12_update_clocks(struct clk_mgr *clk_mgr_base, argument
93 struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base);
102 if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr_base->clks.dispclk_khz)) {
112 clk_mgr_base->clks.dispclk_khz = dce112_set_clock(clk_mgr_base, patched_disp_clk);
114 dm_pp_apply_clock_for_voltage_request(clk_mgr_base->ctx, &clock_voltage_req);
117 if (should_set_clock(safe_to_lower, max_pix_clk, clk_mgr_base->clks.phyclk_khz)) {
120 clk_mgr_base->clks.phyclk_khz = max_pix_clk;
122 dm_pp_apply_clock_for_voltage_request(clk_mgr_base->ctx, &clock_voltage_req);
124 dce11_pplib_apply_display_requirements(clk_mgr_base
[all...]
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dcn10/
H A Damdgpu_rv1_clk_mgr.c130 static void rv1_update_clocks(struct clk_mgr *clk_mgr_base, argument
134 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
135 struct dc *dc = clk_mgr_base->ctx->dc;
167 if (new_clocks->dispclk_khz > clk_mgr_base->clks.dispclk_khz
168 || new_clocks->phyclk_khz > clk_mgr_base->clks.phyclk_khz
169 || new_clocks->fclk_khz > clk_mgr_base->clks.fclk_khz
170 || new_clocks->dcfclk_khz > clk_mgr_base->clks.dcfclk_khz)
173 if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr_base->clks.phyclk_khz)) {
174 clk_mgr_base->clks.phyclk_khz = new_clocks->phyclk_khz;
182 if (should_set_clock(safe_to_lower, new_clocks->fclk_khz, clk_mgr_base
234 rv1_enable_pme_wa(struct clk_mgr *clk_mgr_base) argument
[all...]
H A Drv1_clk_mgr_clk.c57 void rv1_dump_clk_registers(struct clk_state_registers *regs, struct clk_bypass *bypass, struct clk_mgr *clk_mgr_base) argument
59 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dcn20/
H A Damdgpu_dcn20_clk_mgr.c151 void dcn2_update_clocks(struct clk_mgr *clk_mgr_base, argument
155 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
157 struct dc *dc = clk_mgr_base->ctx->dc;
164 struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu;
170 if (clk_mgr_base->clks.dispclk_khz == 0 ||
175 dcn2_read_clocks_from_hw_dentist(clk_mgr_base);
191 if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr_base->clks.phyclk_khz)) {
192 clk_mgr_base->clks.phyclk_khz = new_clocks->phyclk_khz;
194 pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_PHYCLK, clk_mgr_base->clks.phyclk_khz / 1000);
202 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base
342 dcn2_enable_pme_wa(struct clk_mgr *clk_mgr_base) argument
356 dcn2_read_clocks_from_hw_dentist(struct clk_mgr *clk_mgr_base) argument
[all...]
H A Ddcn20_clk_mgr.h57 void dcn2_read_clocks_from_hw_dentist(struct clk_mgr *clk_mgr_base);
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dcn21/
H A Damdgpu_rn_clk_mgr.c101 void rn_update_clocks(struct clk_mgr *clk_mgr_base, argument
105 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
107 struct dc *dc = clk_mgr_base->ctx->dc;
113 struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu;
124 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) {
131 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER;
136 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_MISSION_MODE) {
139 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_MISSION_MODE;
143 if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr_base->clks.phyclk_khz)) {
144 clk_mgr_base
232 rn_dump_clk_registers_internal(struct rn_clk_internal *internal, struct clk_mgr *clk_mgr_base) argument
253 rn_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass, struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info) argument
387 rn_get_clk_states(struct clk_mgr *clk_mgr_base, struct clk_states *s) argument
397 rn_enable_pme_wa(struct clk_mgr *clk_mgr_base) argument
470 rn_notify_wm_ranges(struct clk_mgr *clk_mgr_base) argument
[all...]
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dce110/
H A Damdgpu_dce110_clk_mgr.c253 static void dce11_update_clocks(struct clk_mgr *clk_mgr_base, argument
257 struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base);
265 level_change_req.power_level = dce_get_required_clocks_state(clk_mgr_base, context);
269 if (dm_pp_apply_power_level_change_request(clk_mgr_base->ctx, &level_change_req))
273 if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr_base->clks.dispclk_khz)) {
274 context->bw_ctx.bw.dce.dispclk_khz = dce_set_clock(clk_mgr_base, patched_disp_clk);
275 clk_mgr_base->clks.dispclk_khz = patched_disp_clk;
277 dce11_pplib_apply_display_requirements(clk_mgr_base->ctx->dc, context);
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/
H A Damdgpu_clk_mgr.c177 void dc_destroy_clk_mgr(struct clk_mgr *clk_mgr_base) argument
179 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

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