Lines Matching refs:clk_mgr_base
75 int dce112_set_clock(struct clk_mgr *clk_mgr_base, int requested_clk_khz)
77 struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base);
79 struct dc_bios *bp = clk_mgr_base->ctx->dc_bios;
80 struct dc *dc = clk_mgr_base->ctx->dc;
109 if (!ASICREV_IS_VEGA20_P(clk_mgr_base->ctx->asic_id.hw_internal_rev))
198 static void dce112_update_clocks(struct clk_mgr *clk_mgr_base,
202 struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base);
210 level_change_req.power_level = dce_get_required_clocks_state(clk_mgr_base, context);
214 if (dm_pp_apply_power_level_change_request(clk_mgr_base->ctx, &level_change_req))
218 if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr_base->clks.dispclk_khz)) {
219 patched_disp_clk = dce112_set_clock(clk_mgr_base, patched_disp_clk);
220 clk_mgr_base->clks.dispclk_khz = patched_disp_clk;
222 dce11_pplib_apply_display_requirements(clk_mgr_base->ctx->dc, context);