Lines Matching refs:clk_mgr_base
134 int dce_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base)
136 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
160 int dce12_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base)
162 struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base);
164 return dce_adjust_dp_ref_freq_for_ss(clk_mgr_dce, clk_mgr_base->dprefclk_khz);
200 struct clk_mgr *clk_mgr_base,
203 struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base);
235 struct clk_mgr *clk_mgr_base,
238 struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base);
240 struct dc_bios *bp = clk_mgr_base->ctx->dc_bios;
400 static void dce_update_clocks(struct clk_mgr *clk_mgr_base,
404 struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base);
412 level_change_req.power_level = dce_get_required_clocks_state(clk_mgr_base, context);
416 if (dm_pp_apply_power_level_change_request(clk_mgr_base->ctx, &level_change_req))
420 if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr_base->clks.dispclk_khz)) {
421 patched_disp_clk = dce_set_clock(clk_mgr_base, patched_disp_clk);
422 clk_mgr_base->clks.dispclk_khz = patched_disp_clk;
424 dce_pplib_apply_display_requirements(clk_mgr_base->ctx->dc, context);