1271493Sdelphij/* $NetBSD: dce_clk_mgr.h,v 1.2 2021/12/18 23:45:01 riastradh Exp $ */ 2271493Sdelphij 3271493Sdelphij/* 4271493Sdelphij * Copyright 2012-16 Advanced Micro Devices, Inc. 5271493Sdelphij * 6271493Sdelphij * Permission is hereby granted, free of charge, to any person obtaining a 7271493Sdelphij * copy of this software and associated documentation files (the "Software"), 8271493Sdelphij * to deal in the Software without restriction, including without limitation 9271493Sdelphij * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10271493Sdelphij * and/or sell copies of the Software, and to permit persons to whom the 11271493Sdelphij * Software is furnished to do so, subject to the following conditions: 12271493Sdelphij * 13271493Sdelphij * The above copyright notice and this permission notice shall be included in 14271493Sdelphij * all copies or substantial portions of the Software. 15271493Sdelphij * 16271493Sdelphij * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17271493Sdelphij * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18271493Sdelphij * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19271493Sdelphij * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20271493Sdelphij * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21271493Sdelphij * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22271493Sdelphij * OTHER DEALINGS IN THE SOFTWARE. 23271493Sdelphij * 24271493Sdelphij * Authors: AMD 25273747Sdelphij * 26273747Sdelphij */ 27273747Sdelphij 28271493Sdelphij 29271493Sdelphij#ifndef _DCE_CLK_MGR_H_ 30271493Sdelphij#define _DCE_CLK_MGR_H_ 31271493Sdelphij 32271493Sdelphij#include "dc.h" 33273747Sdelphij 34273747Sdelphij/* functions shared by other dce clk mgrs */ 35271493Sdelphijint dce_adjust_dp_ref_freq_for_ss(struct clk_mgr_internal *clk_mgr_dce, int dp_ref_clk_khz); 36273747Sdelphijint dce_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base); 37273747Sdelphijenum dm_pp_clocks_state dce_get_required_clocks_state( 38273747Sdelphij struct clk_mgr *clk_mgr_base, 39273747Sdelphij struct dc_state *context); 40273747Sdelphij 41273747Sdelphijuint32_t dce_get_max_pixel_clock_for_all_paths(struct dc_state *context); 42273747Sdelphij 43271493Sdelphij 44273747Sdelphijvoid dce_clk_mgr_construct( 45273747Sdelphij struct dc_context *ctx, 46273747Sdelphij struct clk_mgr_internal *clk_mgr_dce); 47273747Sdelphij 48271493Sdelphijvoid dce_clock_read_ss_info(struct clk_mgr_internal *dccg_dce); 49271493Sdelphij 50273747Sdelphijint dce12_get_dp_ref_freq_khz(struct clk_mgr *dccg); 51273747Sdelphij 52273747Sdelphijint dce_set_clock( 53273747Sdelphij struct clk_mgr *clk_mgr_base, 54273747Sdelphij int requested_clk_khz); 55273747Sdelphij 56273747Sdelphij 57271493Sdelphijvoid dce_clk_mgr_destroy(struct clk_mgr **clk_mgr); 58273747Sdelphij 59273747Sdelphijint dentist_get_divider_from_did(int did); 60273747Sdelphij 61273747Sdelphij#endif /* _DCE_CLK_MGR_H_ */ 62271493Sdelphij