clk_mgr/dcn10/amdgpu_rv1_clk_mgr.c

130 static void rv1_update_clocks(struct clk_mgr *clk_mgr_base,
134 	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
135 	struct dc *dc = clk_mgr_base->ctx->dc;
167 	if (new_clocks->dispclk_khz > clk_mgr_base->clks.dispclk_khz
168 			|| new_clocks->phyclk_khz > clk_mgr_base->clks.phyclk_khz
169 			|| new_clocks->fclk_khz > clk_mgr_base->clks.fclk_khz
170 			|| new_clocks->dcfclk_khz > clk_mgr_base->clks.dcfclk_khz)
173 	if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr_base->clks.phyclk_khz)) {
174 		clk_mgr_base->clks.phyclk_khz = new_clocks->phyclk_khz;
182 	if (should_set_clock(safe_to_lower, new_clocks->fclk_khz, clk_mgr_base->clks.fclk_khz)) {
183 		clk_mgr_base->clks.fclk_khz = new_clocks->fclk_khz;
188 	if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) {
189 		clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
194 			new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) {
195 		clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
215 	if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)
216 			|| new_clocks->dispclk_khz == clk_mgr_base->clks.dispclk_khz) {
218 		clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
234 static void rv1_enable_pme_wa(struct clk_mgr *clk_mgr_base)
236 	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);