clk_mgr/dcn20/amdgpu_dcn20_clk_mgr.c

151 void dcn2_update_clocks(struct clk_mgr *clk_mgr_base,
155 	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
157 	struct dc *dc = clk_mgr_base->ctx->dc;
164 	struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu;
170 	if (clk_mgr_base->clks.dispclk_khz == 0 ||
175 		dcn2_read_clocks_from_hw_dentist(clk_mgr_base);
191 	if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr_base->clks.phyclk_khz)) {
192 		clk_mgr_base->clks.phyclk_khz = new_clocks->phyclk_khz;
194 			pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_PHYCLK, clk_mgr_base->clks.phyclk_khz / 1000);
202 	if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) {
203 		clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
205 			pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, clk_mgr_base->clks.dcfclk_khz / 1000);
209 			new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) {
210 		clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
212 			pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu, clk_mgr_base->clks.dcfclk_deep_sleep_khz / 1000);
215 	if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr_base->clks.socclk_khz)) {
216 		clk_mgr_base->clks.socclk_khz = new_clocks->socclk_khz;
218 			pp_smu->set_hard_min_socclk_by_freq(&pp_smu->pp_smu, clk_mgr_base->clks.socclk_khz / 1000);
221 	if (should_update_pstate_support(safe_to_lower, new_clocks->p_state_change_support, clk_mgr_base->clks.p_state_change_support)) {
222 		clk_mgr_base->clks.prev_p_state_change_support = clk_mgr_base->clks.p_state_change_support;
223 		clk_mgr_base->clks.p_state_change_support = new_clocks->p_state_change_support;
225 			pp_smu->set_pstate_handshake_support(&pp_smu->pp_smu, clk_mgr_base->clks.p_state_change_support);
228 	if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr_base->clks.dramclk_khz)) {
229 		clk_mgr_base->clks.dramclk_khz = new_clocks->dramclk_khz;
231 			pp_smu->set_hard_min_uclk_by_freq(&pp_smu->pp_smu, clk_mgr_base->clks.dramclk_khz / 1000);
240 			pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_PIXELCLK, clk_mgr_base->clks.dppclk_khz / 1000);
245 	if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
246 		clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
248 			pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_DISPCLK, clk_mgr_base->clks.dispclk_khz / 1000);
272 			clk_mgr_base->clks.dispclk_khz / 1000 / 7);
342 void dcn2_enable_pme_wa(struct clk_mgr *clk_mgr_base)
344 	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
356 void dcn2_read_clocks_from_hw_dentist(struct clk_mgr *clk_mgr_base)
358 	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
372 		clk_mgr_base->clks.dispclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
375 		clk_mgr_base->clks.dppclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR