1/* $NetBSD: rv1_clk_mgr_clk.c,v 1.2 2021/12/18 23:45:02 riastradh Exp $ */ 2 3/* 4 * Copyright 2012-16 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: AMD 25 * 26 */ 27 28#include <sys/cdefs.h> 29__KERNEL_RCSID(0, "$NetBSD: rv1_clk_mgr_clk.c,v 1.2 2021/12/18 23:45:02 riastradh Exp $"); 30 31#include "reg_helper.h" 32#include "clk_mgr_internal.h" 33#include "rv1_clk_mgr_clk.h" 34 35#include "ip/Discovery/hwid.h" 36#include "ip/Discovery/v1/ip_offset_1.h" 37#include "ip/CLK/clk_10_0_default.h" 38#include "ip/CLK/clk_10_0_offset.h" 39#include "ip/CLK/clk_10_0_reg.h" 40#include "ip/CLK/clk_10_0_sh_mask.h" 41 42#include "dce100/dce_clk_mgr.h" 43 44#define CLK_BASE_INNER(inst) \ 45 CLK_BASE__INST ## inst ## _SEG0 46 47 48#define CLK_REG(reg_name, block, inst)\ 49 CLK_BASE(mm ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \ 50 mm ## block ## _ ## inst ## _ ## reg_name 51 52#define REG(reg_name) \ 53 CLK_REG(reg_name, CLK0, 0) 54 55 56/* Only used by testing framework*/ 57void rv1_dump_clk_registers(struct clk_state_registers *regs, struct clk_bypass *bypass, struct clk_mgr *clk_mgr_base) 58{ 59 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 60 61 regs->CLK0_CLK8_CURRENT_CNT = REG_READ(CLK0_CLK8_CURRENT_CNT) / 10; //dcf clk 62 63 bypass->dcfclk_bypass = REG_READ(CLK0_CLK8_BYPASS_CNTL) & 0x0007; 64 if (bypass->dcfclk_bypass < 0 || bypass->dcfclk_bypass > 4) 65 bypass->dcfclk_bypass = 0; 66 67 68 regs->CLK0_CLK8_DS_CNTL = REG_READ(CLK0_CLK8_DS_CNTL) / 10; //dcf deep sleep divider 69 70 regs->CLK0_CLK8_ALLOW_DS = REG_READ(CLK0_CLK8_ALLOW_DS); //dcf deep sleep allow 71 72 regs->CLK0_CLK10_CURRENT_CNT = REG_READ(CLK0_CLK10_CURRENT_CNT) / 10; //dpref clk 73 74 bypass->dispclk_pypass = REG_READ(CLK0_CLK10_BYPASS_CNTL) & 0x0007; 75 if (bypass->dispclk_pypass < 0 || bypass->dispclk_pypass > 4) 76 bypass->dispclk_pypass = 0; 77 78 regs->CLK0_CLK11_CURRENT_CNT = REG_READ(CLK0_CLK11_CURRENT_CNT) / 10; //disp clk 79 80 bypass->dprefclk_bypass = REG_READ(CLK0_CLK11_BYPASS_CNTL) & 0x0007; 81 if (bypass->dprefclk_bypass < 0 || bypass->dprefclk_bypass > 4) 82 bypass->dprefclk_bypass = 0; 83 84} 85