clk_mgr/dcn21/amdgpu_rn_clk_mgr.c

101 void rn_update_clocks(struct clk_mgr *clk_mgr_base,
105 	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
107 	struct dc *dc = clk_mgr_base->ctx->dc;
113 	struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu;
124 		if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) {
131 				clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER;
136 		if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_MISSION_MODE) {
139 			clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_MISSION_MODE;
143 	if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr_base->clks.phyclk_khz)) {
144 		clk_mgr_base->clks.phyclk_khz = new_clocks->phyclk_khz;
145 		rn_vbios_smu_set_phyclk(clk_mgr, clk_mgr_base->clks.phyclk_khz);
148 	if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) {
149 		clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
150 		rn_vbios_smu_set_hard_min_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_khz);
154 			new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) {
155 		clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
156 		rn_vbios_smu_set_min_deep_sleep_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz);
168 		clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz;
172 	if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
173 		clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
174 		rn_vbios_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz);
182 		rn_vbios_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
186 			rn_vbios_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
196 			clk_mgr_base->clks.dispclk_khz / 1000 / 7);
232 static void rn_dump_clk_registers_internal(struct rn_clk_internal *internal, struct clk_mgr *clk_mgr_base)
234 	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
254 		struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info)
261 	rn_dump_clk_registers_internal(&internal, clk_mgr_base);
387 void rn_get_clk_states(struct clk_mgr *clk_mgr_base, struct clk_states *s)
392 	rn_dump_clk_registers(&sb, clk_mgr_base, &log_info);
397 void rn_enable_pme_wa(struct clk_mgr *clk_mgr_base)
399 	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
470 static void rn_notify_wm_ranges(struct clk_mgr *clk_mgr_base)
472 	struct dc_debug_options *debug = &clk_mgr_base->ctx->dc->debug;
474 	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
478 		build_watermark_ranges(clk_mgr_base->bw_params, &ranges);