/linux-master/drivers/clk/tegra/ |
H A D | clk-utils.c | 10 #define div_mask(w) ((1 << (w)) - 1) macro 39 if (divider_ux1 > div_mask(width)) 40 return div_mask(width);
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H A D | clk-divider.c | 15 #define div_mask(d) ((1 << (d->width)) - 1) macro 17 #define get_max_div(d) div_mask(d) 49 div = (reg >> divider->shift) & div_mask(divider); 96 val &= ~(div_mask(divider) << divider->shift);
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/linux-master/drivers/clk/imx/ |
H A D | clk-fixup-div.c | 12 #define div_mask(d) ((1 << (d->width)) - 1) macro 66 if (value > div_mask(div)) 67 value = div_mask(div); 72 val &= ~(div_mask(div) << div->shift);
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H A D | clk-pllv3.c | 38 * @div_mask: mask of divider bits 52 u32 div_mask; member in struct:clk_pllv3 115 u32 div = (readl_relaxed(pll->base) >> pll->div_shift) & pll->div_mask; 143 val &= ~(pll->div_mask << pll->div_shift); 163 u32 div = readl_relaxed(pll->base) & pll->div_mask; 198 val &= ~pll->div_mask; 220 u32 div = readl_relaxed(pll->base) & pll->div_mask; 285 val &= ~pll->div_mask; 353 mf.mfi = (readl_relaxed(pll->base) & pll->div_mask) ? 22 : 20; 376 val &= ~pll->div_mask; /* clea 411 imx_clk_hw_pllv3(enum imx_pllv3_type type, const char *name, const char *parent_name, void __iomem *base, u32 div_mask) argument [all...] |
H A D | clk.h | 112 #define imx_clk_pllv3(type, name, parent_name, base, div_mask) \ 113 to_clk(imx_clk_hw_pllv3(type, name, parent_name, base, div_mask)) 261 const char *parent_name, void __iomem *base, u32 div_mask);
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/linux-master/drivers/clk/rockchip/ |
H A D | clk-half-divider.c | 11 #define div_mask(width) ((1 << (width)) - 1) macro 29 val &= div_mask(divider->width); 46 maxdiv = div_mask(width); 88 bestdiv = div_mask(width); 118 value = min_t(unsigned int, value, div_mask(divider->width)); 126 val = div_mask(divider->width) << (divider->shift + 16); 129 val &= ~(div_mask(divider->width) << divider->shift);
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/linux-master/drivers/clk/hisilicon/ |
H A D | clkdivider-hi6220.c | 19 #define div_mask(width) ((1 << (width)) - 1) macro 52 val &= div_mask(dclk->width); 82 data &= ~(div_mask(dclk->width) << dclk->shift); 117 max_div = div_mask(width) + 1;
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/linux-master/sound/soc/mediatek/mt8192/ |
H A D | mt8192-afe-clk.c | 412 int div_mask; member in struct:mt8192_mck_div 427 .div_mask = APLL12_CK_DIV0_MASK, 440 .div_mask = APLL12_CK_DIV1_MASK, 453 .div_mask = APLL12_CK_DIV2_MASK, 466 .div_mask = APLL12_CK_DIV3_MASK, 479 .div_mask = APLL12_CK_DIV4_MASK, 492 .div_mask = APLL12_CK_DIVB_MASK, 502 .div_mask = APLL12_CK_DIV5_MASK, 515 .div_mask = APLL12_CK_DIV6_MASK, 528 .div_mask [all...] |
/linux-master/drivers/clk/actions/ |
H A D | owl-factor.h | 58 #define div_mask(d) ((1 << ((d)->width)) - 1) macro
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H A D | owl-factor.c | 157 val &= div_mask(factor_hw); 192 if (val > div_mask(factor_hw)) 193 val = div_mask(factor_hw); 197 reg &= ~(div_mask(factor_hw) << factor_hw->shift);
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/linux-master/include/linux/ |
H A D | sh_clk.h | 60 unsigned int div_mask; member in struct:clk 157 .div_mask = SH_CLK_DIV4_MSK, \ 181 .div_mask = SH_CLK_DIV6_MSK, \ 193 .div_mask = SH_CLK_DIV6_MSK, \
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/linux-master/drivers/clk/ |
H A D | clk-vt8500.c | 23 unsigned int div_mask; member in struct:clk_device 118 u32 div = readl(cdev->div_reg) & cdev->div_mask; 121 if ((cdev->div_mask == 0x3F) && (div & BIT(5))) 126 div = (cdev->div_mask + 1); 150 if ((cdev->div_mask == 0x3F) && (divisor > 31)) { 169 if (divisor == cdev->div_mask + 1) 173 if ((cdev->div_mask == 0x3F) && (divisor > 31)) { 181 if (divisor > cdev->div_mask) { 262 dev_clk->div_mask = 0x1f; 264 of_property_read_u32(node, "divisor-mask", &dev_clk->div_mask); [all...] |
/linux-master/drivers/i2c/busses/ |
H A D | i2c-brcmstb.c | 83 u32 div_mask; member in struct:bsc_clk_param 115 .div_mask = 0 120 .div_mask = 0 125 .div_mask = 0 130 .div_mask = 0 135 .div_mask = BSC_CTL_REG_DIV_CLK_MASK 140 .div_mask = BSC_CTL_REG_DIV_CLK_MASK 145 .div_mask = BSC_CTL_REG_DIV_CLK_MASK 150 .div_mask = BSC_CTL_REG_DIV_CLK_MASK 563 bsc_clk[i].div_mask); [all...] |
/linux-master/sound/soc/fsl/ |
H A D | fsl_mqs.c | 42 * @div_mask: clock divider mask 54 int div_mask; member in struct:fsl_mqs_soc_data 94 mqs_priv->soc->div_mask, 315 .div_mask = MQS_CLK_DIV_MASK, 328 .div_mask = IMX6SX_GPR2_MQS_CLK_DIV_MASK, 341 .div_mask = GENMASK(15, 8),
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/linux-master/drivers/sh/clk/ |
H A D | cpg.c | 123 idx = (sh_clk_read(clk) >> clk->enable_bit) & clk->div_mask; 139 value &= ~(clk->div_mask << clk->enable_bit); 152 if (clk->div_mask == SH_CLK_DIV6_MSK) { 175 val |= clk->div_mask;
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/linux-master/drivers/clk/at91/ |
H A D | clk-peripheral.c | 176 periph->layout->div_mask | periph->layout->cmd | 178 field_prep(periph->layout->div_mask, periph->div) | 245 periph->div = field_get(periph->layout->div_mask, status); 487 if (layout->div_mask)
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H A D | pmc.h | 61 u32 div_mask; member in struct:clk_pll_layout 98 u32 div_mask; member in struct:clk_pcr_layout
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H A D | clk-sam9x60-pll.c | 345 core->layout->div_mask | ena_msk, 367 cdiv = (val & core->layout->div_mask) >> core->layout->div_shift; 454 for (divid = 1; divid < core->layout->div_mask; divid++) { 513 cdiv = (val & core->layout->div_mask) >> core->layout->div_shift; 569 cdiv = (val & core.layout->div_mask) >> core.layout->div_shift;
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H A D | at91sam9n12.c | 76 .div_mask = GENMASK(17, 16),
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H A D | sama5d3.c | 37 .div_mask = GENMASK(17, 16),
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H A D | at91sam9x5.c | 63 .div_mask = GENMASK(17, 16),
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/linux-master/drivers/clk/samsung/ |
H A D | clk-cpu.c | 281 unsigned long div = 0, div_mask = DIV_MASK; local 303 div_mask |= E4210_DIV0_ATB_MASK; 306 exynos_set_safe_div(cpuclk, div, div_mask); 390 unsigned long div = 0, div_mask = DIV_MASK; local 401 exynos_set_safe_div(cpuclk, div, div_mask);
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/linux-master/drivers/clk/mmp/ |
H A D | clk-mix.c | 26 unsigned int div_mask = (1 << mix->reg_info.width_div) - 1; local 31 return div_mask; 33 return 1 << div_mask; 40 return div_mask + 1;
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/linux-master/drivers/clk/nxp/ |
H A D | clk-lpc32xx.c | 920 #define div_mask(width) ((1 << (width)) - 1) macro 952 val &= div_mask(divider->width); 968 bestdiv &= div_mask(divider->width); 988 div_mask(divider->width) << divider->shift, 1475 static void __init lpc32xx_clk_div_quirk(u32 reg, u32 div_mask, u32 gate) argument 1481 if (!(val & div_mask)) { 1483 val |= BIT(__ffs(div_mask)); 1486 regmap_update_bits(clk_regmap, reg, gate | div_mask, val);
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/linux-master/drivers/mfd/ |
H A D | db8500-prcmu.c | 522 u32 div_mask; member in struct:dsiescclk 529 .div_mask = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_MASK, 534 .div_mask = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_MASK, 539 .div_mask = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_MASK, 645 u32 div_mask; local 655 div_mask = PRCM_CLKOCR_CLKODIV0_MASK; 660 div_mask = PRCM_CLKOCR_CLKODIV1_MASK; 671 if (val & div_mask) { 678 if ((val & mask & ~div_mask) != bits) { 1534 div = ((div & dsiescclk[n].div_mask) >> (dsiesccl [all...] |